Impedance matching circuit and method

1. An impedance matching circuit, comprising:

a plurality of buffers each having a variable impedance circuit;

a variable impedance sense control block having an impedance code output as an output; and

a sequencing circuit including a delay element and a flip flop having a clocking input coupled to the delay element, the sequencing circuit coupling the impedance code output of the variable impedance sense control block to the variable impedance circuit of each of the plurality of buffers wherein a plurality of fractional legs codes are updated in a predefined order comprising a largest fractional bit first, at least one integral bit second, and a smallest fractional bit last.

2. The circuit of claim 1 , wherein the plurality of buffers include a data buffer and a clock buffer.

3. The circuit of claim 2 , wherein the flip flop is configured to transmit a bit of the impedance code.

4. The circuit of claim 1 , wherein the sequencing circuit includes a plurality of flip flops coupled to the plurality of buffers.

5. The circuit of claim 1 , wherein the variable impedance sense control block has an update pulse signal.

6. A method of operating an impedance matching system, comprising:

a) sensing an impedance mismatch between a plurality of I/O buffers and a plurality of associated transmission lines and generating an impedance sense code having a plurality of bits; and

b) after generating the impedance sense code, transferring each of the plurality of bits of the impedance sense code in a specific order to each of the plurality of I/O buffers to at least reduce the impedance mismatch, wherein according to the specific order, a largest bit of the plurality of bits is transferred first.

7. The method of claim 6 , wherein the transferring includes transferring the plurality of bits of the impedance sense code to a plurality of flip flops and signaling the plurality of flip flops to transfer the plurality of bits of the impedance sense code in said specific order to the plurality of I/O buffers.

8. The method of claim 7 , wherein transferring further includes delaying a signal to transfer to at least one of the plurality of flip flops.

9. The method of claim 7 , wherein transferring further includes determining a sequence for signaling each of the plurality of flip flops to transfer an individual bit of the impedance sense code.

10. The method of claim 9 , wherein a largest fractional bit flip flop is signaled to transfer first.

11. The method of claim 10 , wherein a smallest fractional bit flip flop is signaled to transfer last.

12. An impedance matching circuit, comprising:

a plurality of buffers each having a variable impedance circuit;

a reference impedance;

a variable impedance sense control block to sense an impedance mismatch between the plurality of buffers and the reference impedance, and in response to the impedance mismatch to generate an impedance code output; and

a sequencing circuit coupling the impedance code output of the variable impedance sense control block to the variable impedance circuit of each of the plurality of buffers wherein a plurality of fractional legs codes are updated in a predefined order comprising a largest fractional bit first, at least one integral bit second, and a smallest fractional bit last, to at least reduce a sensed impedance mismatch, wherein the sequencing circuit includes a delay element and a flip flop having a clocking input coupled to the delay element.

13. The method of claim 6 , wherein transferring further comprises:

transferring an integral largest fraction bit first.

14. The method of claim 13 , wherein transferring further comprises transferring a smallest fractional bit last.

15. The method of claim 6 , wherein transferring further comprises latching each of the plurality of bits of the impedance sense code and delaying at least one of the plurality of bits of the impedance sense code.