Strengthened window-type semiconductor package
View Patent ↗A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.
1. A strengthened window-type semiconductor package, comprising:
a substrate having an upper surface and a lower surface opposed to the upper surface, and formed with at least an opening penetrating through the upper and lower surfaces;
at least a chip having an active surface and a non-active surface opposed to the active surface, wherein the active surface is mounted over the opening on the upper surface of the substrate, allowing a conductive area of the active surface to be exposed to the opening;
a non-conductive material applied over the chip exclusive of the active surface for encapsulating peripheral side of the chip;
a plurality of bonding wires formed through the opening for electrically connecting the conductive area of the chip to the lower surface of the substrate;
an upper encapsulant formed on the upper surface of the substrate for encapsulating the chip and the non-conductive material; and
a lower encapsulant formed on the lower surface of the substrate for encapsulating the bonding wires and sealing the opening.
2. The semiconductor package of claim 1 , further comprising: a plurality of solder balls implanted on the lower surface of the substrate and situated outside the lower encapsulant.
3. The semiconductor package of claim 1 , wherein the non-conductive material is elastic.
4. The semiconductor package of claim 1 , wherein the non-conductive material completely covers the chip except the active surface of the chip.
5. The semiconductor package of claim 1 , wherein the non-conductive material is exposed at top thereof to outside of the upper encapsulant.
6. The semiconductor package of claim 1 , wherein the non-active surface of the chip is exposed to outside of the non-conductive material.
7. The semiconductor package of claim 6 , wherein the non-active surface of the chip is exposed to outside of the upper encapsulant.
8. The semiconductor package of claim 1 , wherein the non-conductive material is applied in a printing manner.
9. The semiconductor package of claim 1 , wherein the non-conductive material is applied in a dispensing manner.
10. The semiconductor package of claim 1 , wherein the conductive area of the chip is formed with a plurality of bond pads where the bonding wires are bonded.
11. The semiconductor package of claim 1 , wherein the upper encapsulant is formed in a molding manner.
12. The semiconductor package of claim 1 , wherein the lower encapsulant is formed in a printing manner.
13. The semiconductor package of claim 2 , wherein height of the solder balls is larger than thickness of the lower encapsulant protruding from the lower surface of the substrate.