Multi-bank content addressable memory (CAM) devices having segment-based priority resolution circuits therein and methods operating same
View Patent ↗Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.
1. A content addressable memory (CAM) device, comprising:
first and second segments of CAM array blocks; and
a hierarchical priority resolution circuit that is disposed between said first and second segments of CAM array blocks and comprises:
a soft priority resolution circuit that is configured to resolve a parallel soft priority competition between a first plurality of active hit signals generated by the first segment of CAM array blocks and a second plurality of active hit signals generated by the second segment of CAM array blocks; and
first and second hard priority resolution circuits that are electrically coupled to first and second outputs, respectively, of said soft priority resolution circuit.
2. The CAM device of claim 1 , wherein said first hard priority resolution circuit is configured to resolve competing hard priorities between two or more of the first plurality of active hit signals having equivalent highest soft priorities amongst all of the first and second pluralities of active hit signals; and wherein said second hard priority resolution circuit is configured to resolve competing hard priorities between two or more of the second plurality of active hit signals having equivalent highest soft priorities amongst all of the first and second pluralities of active hit signals.
3. The CAM device of claim 2 , wherein all of the CAM array blocks in said first segment of CAM array blocks have a higher hard priority than all of the CAM array blocks in said second segment of CAM array blocks.
4. The CAM device of claim 1 , wherein said first hard priority resolution circuit is configured to resolve competing hard priorities between two or more of the first plurality of active hit signals having equivalent highest soft priorities amongst all of the first and second pluralities of active hit signals.
5. A content addressable memory (CAM) device, comprising:
a bank of CAM array blocks, said bank comprising:
a plurality of first segments of CAM array blocks and a plurality of second segments of CAM array blocks; and
a soft/hard priority resolution circuit that is disposed between the plurality of first segments of CAM array blocks and the plurality of second segments of CAM array blocks and is configured to resolve a segment-staged priority competition between active hit signals generated by respective CAM array blocks in said bank including active hit signals having equivalent soft priorities.
6. The CAM device of claim 5 , wherein said soft/hard priority resolution circuit is divided into a plurality of segments that are each configured to receive hit signals from a respective one of the plurality of first segments of CAM array blocks and a respective one of the plurality of second segments of CAM array blocks.
7. The CAM device of claim 5 , wherein the plurality of first segments of CAM array blocks include at least first and second top segments of CAM array blocks; wherein the plurality of second segments of CAM array blocks include at least first and second bottom segments of CAM array blocks; and wherein said soft/hard priority resolution circuit is divided into at least a first segment that receives hit signals from the first top and bottom segments of CAM array blocks and a second segment that receives hit signals from the second top and bottom segments of CAM array blocks.
8. The CAM device of claim 7 , wherein the first segment of said soft/hard priority resolution circuit is configured to simultaneously resolve competing soft priorities between active hit signals generated by the first top and bottom segments of CAM array blocks; and wherein the second segment of said soft/hard priority resolution circuit is configured to simultaneously resolve competing soft priorities between active hit signals generated by the second top and bottom segments of CAM array blocks.
9. The CAM device of claim 8 , wherein all of the CAM array blocks in the first top segment of CAM array blocks have a higher hard priority than all of the CAM array blocks in the first bottom segment of CAM array blocks or vice-versa.
10. The CAM device of claim 9 , wherein all of the CAM array blocks in the second top segment of CAM array blocks have a higher hard priority than all of the CAM array blocks in the first bottom segment of CAM array blocks or vice-versa.
11. The CAM device of claim 10 , wherein all of the CAM array blocks in the plurality of first segments of CAM array blocks have a higher hard priority than all of the CAM array blocks in the plurality of second segments of CAM array blocks or vice versa.
12. A content addressable memory (CAM) device, comprising:
a priority resolution circuit configured to resolve competing soft priorities between a first plurality of active hit signals that are generated adjacent a first side of said priority resolution circuit and a second plurality of active hit signals that are generated adjacent a second side of said priority resolution circuit that is opposite the first side, said priority resolution circuit further configured to resolve competing priorities between at least two of the first and second plurality of active hit signals having equivalent soft priority.
13. The CAM device of claim 12 , wherein said priority resolution circuit is configured to hierarchically resolve competing soft priorities between the first and second pluralities of active hit signals according to numeric significance.
14. The CAM device of claim 13 , wherein said priority resolution circuit is configured to resolve competing hard priorities between two or more of the first plurality of active hit signals having equivalent highest soft priorities by identifying which of the two or more of the first plurality of active hits signals has the highest relative hard priority.
15. The CAM device of claim 14 , wherein said priority resolution circuit is configured to resolve competing hard priorities between two or more of the second plurality of active hit signals having equivalent highest soft priorities by identifying which of the two or more of the second plurality of active hits signals has the highest relative hard priority.
16. The CAM device of claim 15 , wherein said priority resolution circuit comprises:
a first hard priority resolution stage that is electrically coupled to a first plurality of outputs of said LSB soft priority resolution stage; and
a second hard priority resolution stage that is electrically coupled to a second plurality of outputs of said LSB soft priority resolution stage.
17. The CAM device of claim 16 , wherein the first and second pluralities of outputs of said LSB soft priority resolution stage are arranged in alternating sequence.
18. The CAM device of claim 13 , wherein said priority resolution circuit comprises a MSB soft priority resolution stage and a LSB soft priority resolution stage.
19. The CAM device of claim 12 , further comprising:
a first plurality of CAM array blocks that have respective first soft priorities assigned thereto and are arranged adjacent the first side of said priority resolution circuit;
a second plurality of CAM array blocks that have respective second soft priorities assigned thereto and are arranged adjacent the second side of said priority resolution circuit; and
wherein said priority resolution circuit comprises a first plurality of registers that retain the first soft priorities assigned to said first plurality of CAM array blocks and a second plurality of registers that retain the second soft priorities assigned to said second plurality of CAM array blocks.
20. A content addressable memory (CAM) device, comprising:
a first plurality of CAM array blocks having respective soft priorities assigned thereto;
a second plurality of CAM array blocks having respective soft priorities assigned thereto; and
a hierarchical priority resolution circuit that is disposed between said first and second pluralities of CAM array blocks and is configured to identify a highest priority one of said first and second pluralities of CAM array blocks having respective matching entries therein during a search operation, by simultaneously evaluating the soft priorities of said first plurality of CAM array blocks and said second plurality of CAM array blocks according to numeric significance and resolving competing soft priorities that are equivalent.
21. A content addressable memory (CAM) device, comprising:
a first segment of N CAM array blocks, where N is an integer;
a second segment of N CAM array blocks; and
a priority resolution circuit that is disposed between said first and second segments of CAM array blocks, said priority resolution circuit comprising 2N priority resolution columns therein that resolve competing soft priorities between active hit signals generated by said first and second segments of CAM array blocks in parallel and configured to support multiple active hit signals having the same soft priority.
22. The CAM device of claim 21 , wherein one half of the 2N priority resolution columns resolve competing hard priorities between active hit signals generated by said first segment of CAM array blocks; and wherein another half of the 2N priority resolution columns resolve competing hard priorities between active hit signals generated by said second segment of CAM array blocks.
23. The CAM device of claim 22 , wherein all of the CAM array blocks in said first segment having a higher hard priority than all of the CAM array blocks in said second segment.