Semiconductor device with copper wirings
View Patent ↗A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.
1. A semiconductor device comprising:
a silicon substrate having an n-type region;
a gate insulating film formed on the n-type region, said gate insulating film being comprised from nitrogen-containing silicon oxide;
a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon;
p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode;
side wall spacers formed on side walls of said gate electrode, using silicon oxide;
an interlayer insulating film having a planarized surface layer of silicon oxide and covering said gate electrode and side wall spacers;
a wiring trench formed in said interlayer insulating film from the planarized surface layer to an inside thereof;
a copper wiring pattern including an underlying barrier layer and an upper level copper region, said copper wiring pattern being filled in said wiring trench; and
a silicon carbide layer formed on the planarized surface layer of said interlayer insulating film to cover the upper level copper region of said copper wiring pattern.
2. A semiconductor device according to claim 1 , wherein said sidewall spacer is made of a single silicon oxide layer.
3. A semiconductor device according to claim 1 , wherein said side wall spacer is made of a lamination of a silicon nitride layer and an upper level silicon oxide layer.
4. A semiconductor device according to claim 1 , wherein silicon oxide of said gate insulating film contains nitrogen of at least 1 at. %.
5. A semiconductor device according to claim 1 , wherein said interlayer insulating film includes an etch stopper layer made of silicon nitride as a lowermost layer.
6. A semiconductor device according to claim 5 , wherein said interlayer insulating film includes a lower interlayer insulating film including the etch stopper layer and an upper interlayer insulating film including a low dielectric constant insulating layer having a dielectric constant lower than that of silicon oxide.
7. A semiconductor device according to claim 6 , wherein the low dielectric constant insulating film is an organic insulating layer.
8. A semiconductor device according to claim 1 , wherein said gate insulating film includes one of: a lamination of a silicon oxide layer and a silicon nitride layer; a silicon oxynitride layer having an increased nitrogen concentration in a surface layer; a lamination of a silicon oxide layer including nitrogen and an oxide layer having a dielectric constant higher than silicon nitride; and a lamination of a silicon nitride layer and an oxide layer having a dielectric constant higher than silicon nitride.
9. A semiconductor device comprising:
a silicon substrate having an n-type region;
a gate insulating film formed on the n-type region, said gate insulating film comprising a lamination structure having two or more layers with different dielectric constants;
a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon;
p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode;
an interlayer insulating film having a planarized surface layer of silicon oxide and covering said gate electrode;
a wiring trench formed in said interlayer insulating film from the planarized surface layer to an inside thereof;
a copper wiring pattern including an underlying barrier layer and an upper level copper region filled in said wiring trench; and
a copper diffusion prevention insulating film not containing nitrogen formed on the upper level copper region of said copper wiring pattern, so as to cover the upper level copper region.
10. A semiconductor device according to claim 9 , wherein said interlayer insulating film includes a lower interlayer insulating film including an etch stopper layer and an upper interlayer insulating film including a low dielectric constant insulating layer having a dielectric constant lower than that of silicon oxide.
11. A semiconductor device according to claim 10 , wherein the low dielectric constant insulating film is an organic insulating layer.
12. A semiconductor device according to claim 9 , wherein said gate insulating film includes a lower insulating film containing nitrogen less than 1 at. % and an upper insulating film containing nitrogen at least 1 at. %.
13. A semiconductor device according to claim 1 , wherein the silicon carbide layer is a layer in which concentration of Si—H couplings is suppressed.
14. A semiconductor device according to claim 5 , wherein the silicon carbide layer is a layer in which concentration of Si—H couplings is suppressed.