Structure of a capacitive element of a booster circuit included in a semiconductor device and method of manufacturing such a structure
View Patent ↗A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.
1. A semiconductor device comprising:
a semiconductor substrate;
a device isolation film disposed on said semiconductor substrate;
a lower electrode disposed on said device isolation film;
trenches formed in said device isolation film in surrounding relation to said lower electrode and having a bottom portion that is lower than a bottom portion of said lower electrode;
trench-embedded insulators embedded in said trenches;
an insulating film disposed on said lower electrode; and
an upper electrode disposed over said lower electrode with said insulating film interposed therebetween;
wherein said lower electrode, said insulating film, and said upper electrode jointly make up a capacitive element.
2. A semiconductor device comprising:
a semiconductor substrate;
a device isolation film disposed on said semiconductor substrate;
a lower electrode disposed on said device isolation film;
a trench formed in said device isolation film in surrounding relation to said lower electrode and having a bottom portion that is lower than a bottom portion of said lower electrode;
a trench-embedded insulator embedded in said trench;
an insulating film disposed on said lower electrode; and
an upper electrode disposed over said lower electrode with said insulating film interposed therebetween;
wherein said lower electrode, said insulating film, and said upper electrode jointly make up a capacitive element, and
wherein said trench-embedded insulator has an upper surface positioned higher than an upper surface of said lower electrode.
3. The semiconductor device comprising:
a semiconductor substrate;
a device isolation film disposed on said semiconductor substrate;
a lower electrode disposed on said device isolation film;
trenches formed in said device isolation film in surrounding relation to said lower electrode and having a bottom portion that is lower than a bottom portion of said lower electrode;
trench-embedded insulators embedded in said trenches;
an insulating film disposed on said lower electrode; and
an upper electrode disposed over said lower electrode with said insulating film interposed therebetween;
wherein said lower electrode, said insulating film, and said upper electrode jointly make up a capacitive element, and
wherein said capacitive element comprises a capacitor of a charge pump circuit.
4. The semiconductor device according to claim 1 , wherein said semiconductor device is a nonvolatile memory device having a plurality of memory cells each comprising a channel region, a floating gate electrode disposed over said channel region with a gate insulating film interposed therebetween, and a control gate electrode disposed over said floating gate electrode with an insulating film interposed therebetween, and wherein elements of each of the memory cells are isolated by said trench-embedded insulators.
5. A semiconductor device comprising:
a semiconductor substrate;
a device isolation film disposed on said semiconductor substrate;
a lower electrode disposed on said device isolation film;
a trench formed in said device isolation film in surrounding relation to said lower electrode and having a bottom portion that is lower than a bottom portion of said lower electrode;
a trench-embedded insulator embedded in said trench;
an insulating film disposed on said lower electrode; and
an upper electrode disposed over said lower electrode with said insulating film interposed therebetween;
wherein said lower electrode, said insulating film, and said upper electrode jointly make up a capacitive element,
wherein said semiconductor device is a nonvolatile memory device having a plurality of memory cells each comprising a channel region, a floating gate electrode disposed over said channel region with a gate insulating film interposed therebetween, and a control gate electrode disposed over said floating gate electrode with an insulating film interposed therebetween, and wherein elements of each of the memory cells are isolated by said trench-embedded insulator, and
wherein said trench-embedded insulator has an upper surface positioned higher than an upper surface of said lower electrode.
6. The semiconductor device comprising:
a semiconductor substrate;
a device isolation film disposed on said semiconductor substrate;
a lower electrode disposed on said device isolation film;
a trench formed in said device isolation film in surrounding relation to said lower electrode and having a bottom portion that is lower than a bottom portion of said lower electrode;
a trench-embedded insulator embedded in said trench;
an insulating film disposed on said lower electrode; and
an upper electrode disposed over said lower electrode with said insulating film interposed therebetween;
wherein said lower electrode, said insulating film, and said upper electrode jointly make up a capacitive element,
wherein said semiconductor device is a nonvolatile memory device having a plurality of memory cells each comprising a channel region, a floating gate electrode disposed over said channel region with a gate insulating film interposed therebetween, and a control gate electrode disposed over said floating gate electrode with an insulating film interposed therebetween, and wherein elements of each of the memory cells are isolated by said trench-embedded insulator, wherein said trench-embedded insulator has an upper surface positioned higher than an upper surface of said lower electrode, and
wherein said capacitive element comprises a capacitor of a charge pump circuit.