Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams
View Patent ↗An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.
1. An apparatus comprising:
a first receive circuit configured to couple to a first interface to receive a first plurality of packets, wherein the first receive circuit is configured, for each packet of the first plurality of packets, to select a destination from one of a plurality of destinations and wherein the first receive circuit is further configured to select, for each packet, one of the plurality of virtual channels on a destination of that packet;
a second receive circuit configured to couple to a second interface to receive a second plurality of packets, wherein the second receive circuit is configured, for each packet of the second plurality of packets, to select a destination from one of the plurality of destinations and wherein the second receive circuit is further configured to select, for each packet, one of a plurality of virtual channels on the destination of that packet;
a plurality of transmit circuits configured to transmit packets on respective interfaces, wherein the plurality of destinations comprises the plurality of transmit circuits;
a packet direct memory access (DMA) circuit, wherein the packet DMA circuit is configured to communicate packets to and from a memory controller, and wherein the packet DMA circuit is one of the plurality of destinations; and
a switch coupled to the first receive circuit, the second receive circuit, and the plurality of destinations, wherein the switch is configured to couple the first receive circuit and the second receive circuit to select ones of the plurality of destinations to convey packets from the first receive circuit and the second receive circuit to the select ones of the plurality of destinations;
wherein the first receive circuit, the second receive circuit, the plurality of destinations, and the switch are integrated onto an integrated circuit.
2. The apparatus as recited in claim 1 wherein the plurality of transmit circuits include a first transmit circuit configured to couple to the first interface and a second transmit circuit configured to couple to the second interface.
3. The apparatus as recited in claim 1 wherein, if: (i) the first receive circuit receives a first packet for a first destination and a first virtual channel on the first destination; and (ii) the second receive circuit receives a second packet for the first destination and the first virtual channel on the first destination; the switch is configured to select a selected one of the first receive circuit or the second receive circuit to transmit the first packet or the second packet, and wherein the switch is configured to inhibit selecting the other one of the first receive circuit or the second receive circuit until the selected one reaches a packet boundary.
4. The apparatus as recited in claim 1 wherein the first receive circuit is programmable to select the destination for each of the first plurality of packets.
5. The apparatus as recited in claim 4 wherein the first receive circuit comprises a hash and route circuit coupled to receive at least a portion of each of the plurality of packets and a virtual channel on which that packet is received, and wherein the hash and route circuit is programmable to select the destination responsive to one or both of the portion of that packet and the virtual channel on which that packet is received.
6. The apparatus as recited in claim 1 further comprising the memory controller integrated onto the integrated circuit, wherein the memory controller is configured to couple to a memory, and wherein the packet DMA circuit is configured to transmit packets received by the packet DMA circuit to the memory controller for storage in the memory.
7. The apparatus as recited in claim 6 wherein the packet DMA circuit is further configured to transmit packets to one of the plurality of destinations.
8. The apparatus as recited in claim 7 wherein the switch is configured to couple the packet DMA circuit to the one of the plurality of destinations.
9. The apparatus as recited in claim 1 wherein the first receive circuit is configured to select a first destination of the plurality of destinations for a first packet of the first plurality of packets, and wherein the first receive circuit is configured to select a second destination of the plurality of destinations for a second packet of the first plurality of packets, wherein the first destination is different from the second destination.
10. A method comprising:
receiving a first plurality of packets in a first receive circuit of an integrated circuit;
selecting a destination from one of a plurality of destinations for each packet of the first plurality of packets by selecting one of a plurality of virtual channels on a destination of that packet;
receiving a second plurality of packets in a second receive circuit of the integrated circuit;
selecting a destination from one of the plurality of destinations for each packet of the second plurality of packets by selecting one of a plurality of virtual channels on the destination of that packet;
coupling the first receive circuit and the second receive circuit to select ones of the plurality of destinations via a switch in the integrated circuit to convey packets, wherein the integrated circuit includes a plurality of transmit circuits configured to transmit packets on respective interfaces of the integrated circuit, and wherein the plurality of destinations includes the plurality of transmit circuits, and wherein the integrated circuit further includes a packet direct memory access (DMA) Circuit, wherein the packet DMA circuit is configured to communicate packets to and from a memory controller, and wherein the packet DMA circuit is one of the plurality of destinations.
11. The method as recited in claim 10 further comprising, if: (i) the first receive circuit receives a first packet for a first destination and a first virtual channel on the first destination; and (ii) the second receive circuit receives a second packet for the first destination and the first virtual channel on the first destination:
selecting a selected one of the first receive circuit or the second receive circuit to transmit the first packet or the second packet; and
inhibiting selecting the other one of the first receive circuit or the second receive circuit until the selected one reaches a packet boundary.
12. The method as recited in claim 10 further comprising programming the first receive circuit to select the destination for each of the first plurality of packets.
13. The method as recited in claim 12 wherein the first receive circuit comprises a hash and route circuit coupled to receive at least a portion of each of the plurality of packets and a virtual channel on which that packet is received, and wherein programming the first transmit circuit to select the destination for each of the first plurality of packets comprises programming the hash and route circuit to select the destination responsive to one or both of the portion of that packet and the virtual channel on which that packet is received.
14. A computer-readable storage medium embodying computer executable data structures to perform a function of a circuit, comprising:
a first receive circuit configured to couple to a first interface to receive a first plurality of packets, wherein the first receive circuit is configured, for each packet of the first plurality of packets, to select a destination from one of a plurality of destinations and wherein the first receive circuit is further configured to select, for each packet, one of a plurality of virtual channels on the destination of that packet;
a second receive circuit configured to couple to a second interface to receive a second plurality of packets, wherein the second receive circuit is configured, for each packet of the second plurality of packets, to select a destination from one of the plurality of destinations and wherein the second receive circuit is further configured to select, for each packet, one of a plurality of virtual channels on the destination of that packet;
a plurality of transmit circuits configured to transmit packets on respective interfaces, wherein the plurality of destinations comprises the plurality of transmit circuits;
a packet direct memory access (DMA) circuit, wherein the packet DMA circuit is configured to communicate packets to and from a memory controller, and wherein the packet DMA circuit is one of the plurality of destinations; and
a switch coupled to the first receive circuit, the second receive circuit, and the plurality of destinations, wherein the switch is configured to couple the first receive circuit and the second receive circuit to select ones of the plurality of destinations to convey packets from the first receive circuit and the second receive circuit to the select ones of the plurality of destinations;
wherein the first receive circuit, the second receive circuit, the plurality of destinations, and the switch are integrated onto an integrated circuit.
15. The computer-readable storage medium as recited in claim 14 wherein the plurality of transmit circuits include a first transmit circuit configured to couple to the first interface and a second transmit circuit configured to couple to the second interface.
16. The computer-readable storage medium as recited in claim 14 wherein, if: (i) the first receive circuit receives a first packet for a first destination and a first virtual channel on the first destination; and (ii) the second receive circuit receives a second packet for the first destination and the first virtual channel on the first destination; the switch is configured to select a selected one of the first receive circuit or the second receive circuit to transmit the first packet or the second packet, and wherein the switch is configured to inhibit selecting the other one of the first receive circuit or the second receive circuit until the selected one reaches a packet boundary.
17. The computer-readable storage medium as recited in claim 14 wherein the first receive circuit is programmable to select the destination for each of the first plurality of packets.
18. The computer-readable storage medium as recited in claim 17 wherein the first receive circuit comprises a hash and route circuit coupled to receive at least a portion of each of the plurality of packets and a virtual channel on which that packet is received, and wherein the hash and route circuit is programmable to select the destination responsive to one or both of the portion of that packet and the virtual channel on which that packet is received.
19. The computer-readable storage medium as recited in claim 14 wherein the packet DMA circuit is further configured to transmit packets to one of the plurality of destinations.
20. The computer-readable storage medium as recited in claim 19 wherein the switch is configured to couple the packet DMA circuit to the one of the plurality of destinations.
21. The computer-readable storage medium as recited in claim 14 wherein the first receive circuit is configured to select a first destination of the plurality of destinations for a first packet of the first plurality of packets, and wherein the first receive circuit is configured to select a second destination of the plurality of destinations for a second packet of the first plurality of packets, wherein the first destination is different from the second destination.