IP Library Granted Patent US 6,864,110
Granted Patent B2
US 6,864,110 · App. 10/277,285 · Granted Mar 8, 2005

Electrophoretic processes for the selective deposition of materials on a semiconducting device

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Quick Facts
Patent No.
US 6,864,110
App. No.
10/277,285
Granted
Mar 8, 2005
Kind
B2
Abstract

The present invention provides a process and apparatus for selectively depositing materials on a semiconductor device, such as depositing phosphors or other optical materials on a light emitting diode (LED), using an electrophoretic deposition process. The semiconductor device comprises a p-side and an n-side. A first biasing voltage is applied between an anode and the p-side of the semiconductor device. A second biasing voltage is applied between the p-side and the n-side of the semiconductor device. The relative biasing of the p-side and the n-side determines where coating is deposited on the semiconductor device. An optional pre-coating process is used to deposit a high resistivity dielectric material, such as silica, on the semiconductor device. The pre-coating can even the electric field on the surface of the semiconductor device, where local features such as metal connections or passivation layers disturb the electric field during phosphor deposition without pre-coating.

Claims (27)

1. A method for coating a semiconductor device, the semiconductor device having a p-side and an n-side, the method comprising:

providing a bath, the bath containing suspended particles;

providing an anode, the anode disposed in the bath;

disposing the semiconductor device in the bath;

applying a first biasing voltage between the anode and the p-side, the anode held at a positive voltage with respect to the p-side; and

applying a second biasing voltage between the p-side and the n-side.

2. The method of claim 1 wherein the second biasing voltage is selected from the group consisting of reverse bias, zero bias, and forward bias.

3. The method of claim 1 wherein applying a second biasing voltage between the p-side and the n-side further comprises applying a second biasing voltage switchable between a reverse bias, a zero bias, and a forward bias.

4. The method of claim 1 wherein applying a second biasing voltage between the p-side and the n-side comprises applying a voltage between the anode and the n-side.

5. The method of claim 1 wherein the semiconductor device is selected from the group consisting of a light emitting diode (LED), an electroluminescent device, a laser device, a pnp transistor, an npn transistor, a Charge-Coupled Device CCD, a CMOS imager, an amorphous silicon device, an X-ray imager, a phototransistor, a semiconductor, and a semiconductor device array.

6. The method of claim 1 wherein the semiconductor device is one of a plurality of semiconductor devices disposed in the bath.

7. The method of claim 1 further comprising pre-coating the semiconductor device.

8. The method of claim 7 wherein pre-coating the semiconductor device comprises pre-coating the semiconductor device with a high resistivity dielectric material coating.

9. The method of claim 1 further comprising masking the semiconductor device.

10. The method of claim 1 wherein the suspended particles are phosphor particles.

11. The method of claim 1 wherein the suspended particles are selected from the group consisting of optical materials, high resistivity dielectric materials, phosphor, silica, titanium dioxide, and combinations thereof.

12. The method of claim 1 wherein applying a second biasing voltage between the p-side and the n-side further comprises applying a second biasing voltage between the p-side and the n-side to cause the semiconductor device to emit light, the light ionizing the bath.

13. A method for coating a light emitting diode, the light emitting diode having a p-side and an n-side, the method comprising:

providing a bath, the bath containing phosphor particles and magnesium nitrate;

providing an anode, the anode disposed in the bath;

disposing the light emitting diode in the bath;

applying a first biasing voltage between the anode and the p-side, the anode held at a positive voltage with respect to the p-side; and

applying a second biasing voltage between the p-side and the n-side.

14. The method of claim 13 wherein applying a second biasing voltage between the p-side and the n-side further comprises switching the second biasing voltage between a reverse bias, a zero bias, and a forward bias.

15. The method of claim 13 wherein applying a second biasing voltage between the p-side and the n-side comprises applying a voltage between the anode and the n-side.

16. The method of claim 13 further comprising pre-coating the light emitting diode with silica.

17. The method of claim 13 further comprising masking the semiconductor device.

Assignments (11)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME TO PHOSPHORTECH CORPORATION AND AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. PREVIOUSLY RECORDED ON REEL 020866 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded May 9, 2008
From: AGILENT TECHNOLOGIES, INC.; PHOSPHORTECH CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; PHOSPHORTECH CORPORATION
Reel/Frame 020919/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2008
From: AGILENT TECHNOLOGIES, INC.; PHOSPHORTECH CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 020866/0628 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2003
From: SUMMERS, CHRISTOPHER J.; MENKARA, HISHAM; CHUA, BEE YIN JANET
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014085/0596 →
CORRECTIVE ASSIGNMENT TO ADD AN ASSIGNEE'S NAME, PREVIOUSLY RECORDED AT REEL 013391 FRAME 0858. (ASSIGNMENT OF ASSIGNOR'S INTEREST) Recorded Mar 12, 2003
From: SUMMERS, CHRISTOPHER J.; MENKARA, HISHAM; CHUA, BEE YIN JANET
To: AGILENT TECHNOLOGIES, INC.; PHOSPHOR TECH CORPORATION
Reel/Frame 013476/0958 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2003
From: SUMMERS, CHRISTOPHER J.; MENKARA, HISHAM; CHUA, BEE YIN JANET
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 013391/0858 →