On-chip PLL locked frequency determination method and system
View Patent ↗The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.
1. A semiconductor integrated circuit comprising at least one frequency determining unit, the frequency determining unit comprising:
a plurality of delay elements;
one or more input latching devices coupled to receive a test signal and a clock signal, the one or more input latching devices configured to latch the test signal and provide the latched test signal to the plurality of delay elements; and
one or more output latching devices coupled to the delay elements to receive the clock signal and a delayed version of the latched test signal after the test signal is delayed by the delay elements, the one or more output latching devices to latch the delayed version of the latched test signal to produce an output signal.
2. The semiconductor integrated circuit of claim 1 , further comprising:
a first selector having a plurality of inputs coupled to respective delay elements; and
an output to provide the delayed version of the latched test signal to the one or more output latching devices.
3. The semiconductor integrated circuit of claim 1 , further comprising:
a second selector coupled to the delay elements, configured to select the one or more input latching devices for the test signal.
4. The semiconductor integrated circuit of claim 1 , wherein
the one or more input latching devices latch the test signal at a first transition of the clock signal; and
the one or more output latching devices latch the delayed version of the latched test signal at a second transition of the clock signal.
5. The semiconductor integrated circuit of claim 4 , further comprising:
a control unit coupled to the frequency determining unit, configured to provide the test signal.
6. The semiconductor integrated circuit of claim 5 , wherein the control unit is further configured to
receive the output signal; and
determine a locked frequency of the PLL.
7. The semiconductor integrated circuit of claim 5 , wherein the control unit is further configured to provide select signals for a first selector and a second selector.
8. A system for determining locked frequency of a phase locked loop (PLL), in an integrated circuit, comprising:
means for selecting at least one of a plurality of delay units;
means for providing an input test signal using the output of the PLL for the selected delay unit to output a delayed input test signal; and
means for determining whether the delayed input test signal matches the input test signal.
9. The system of claim 8 , further comprising:
means for iteratively repeating the steps of selecting, providing and determining until the delayed input test signal matches the input test signal.