Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types

1. A phase controlling semiconductor manufacturing resolution enhancement method comprising:

providing a transparent substrate;

forming a first resolution enhancement structure over a first portion of the transparent substrate; and

forming a second resolution enhancement structure over a second portion of the transparent substrate, the second resolution enhancement structure different from the first resolution enhancement structure, forming the second resolution enhancement structure further comprises placing a single partially transparent film on the transparent substrate and an opaque film on the partially transparent film; and

processing the opaque film to form a mask.

2. The method as claimed in claim 1 additionally comprising:

providing a first film on the first portion of the transparent substrate having the first resolution enhancement structure formed therein; and

providing a second film on the second portion of the transparent substrate having the second resolution enhancement structure formed therein.

3. The method as claimed in claim 1 additionally comprising;

providing a first film on the transparent substrate;

providing a second film on the first film;

removing a portion of the second film to form the first resolution enhancement structure in the first film; and

forming the second resolution enhancement structure in the first and second films.

4. The method as claimed in claim 1 wherein:

forming the first resolution enhancement structure uses a structure selected from a group consisting of a binary mask portion, a phase shift mask portion, a proximity effect mask portion, an alternating phase shift mask portion, an attenuated phase shift mask portion, and a combination thereof.

5. The method as claimed in claim 1 wherein:

forming the first resolution enhancement structure forms the structure over a core portion of the mask; and

forming the second resolution enhancement structure forms the structure over a periphery portion of the mask.

6. The method as claimed in claim 1 wherein: placing the mask in a lithography system.

7. The method as claimed in claim 1 additionally comprising:

forming a semiconductor substrate having tightly spaced structures on the first portion and isolated structures on the second portion of the semiconductor substrate.

8. A phase controlling semiconductor manufacturing enhancement method comprising:

providing a light-transparent substrate;

forming a first resolution enhancement structure over a first portion of the light-transparent substrate; and

forming a second resolution enhancement structure over a second portion of the light-transparent substrate, the second resolution enhancement structure different from the first resolution enhancement structure, the second resolution enhancement structure using a single partially light-transparent film on the light-transparent substrate and an opaque film on the partially light-transparent film; and

processing the opaque film to form a patterned mask.

9. The method as claimed in claim 8 additionally comprising:

providing an opaque film on the first portion of the light-transparent substrate having the first resolution enhancement structure formed therein; and

providing a partially transparent film on the second portion of the light-transparent substrate having the second resolution enhancement structure formed therein.

10. The method as claimed in claim 8 additionally comprising:

providing a partially transparent film on the transparent substrate;

providing an opaque film on the partially transparent film;

removing a portion of the opaque film to form the first resolution enhancement structure in the partially transparent film; and

forming the second resolution enhancement structure in the partially transparent and opaque films.

11. The method as claimed in claim 8 wherein:

forming the first resolution enhancement structure uses a structure selected from a group consisting of a binary mask portion, a phase shift mask portion, a proximity effect mask portion, an alternating phase shift mask portion, an attenuated phase shift mask portion, and a combination thereof; and

forming the second resolution enhancement structure uses a structure selected from a group consisting of a binary mask portion, a phase shift mask portion, a proximity effect mask portion, an alternating phase shift mask portion, an attenuated phase shift mask portion, and a combination thereof.

12. The method as claimed in claim 8 wherein:

forming the first resolution enhancement structure forms the structure over a core portion of the mask; and

forming the second resolution enhancement structure forms the structure over a periphery portion of the mask.

13. The method as claimed in claim 8 wherein:

placing the mask in a photolithography system.

14. The method as claimed in claim 8 additionally comprising:

forming a semiconductor substrate having proximally spaced structures on the first portion in a core portion of the semiconductor substrate and distally spaced structures on the second portion in a peripheral portion of the semiconductor substrate.

15. A phase controlling semiconductor manufacturing resolution enhancement system comprising:

a transparent substrate;

a first resolution enhancement structure over a first portion of the transparent substrate; and

a second resolution enhancement structure over a second portion of the transparent substrate, the second resolution enhancement structure different from the first resolution enhancement structure, the second resolution enhancement structure has a single partially transparent film on the transparent substrate and an opaque film on the partially transparent film; and

the transparent substrate, the first resolution enhancement structure, and the second resolution enhancement structure form a mask.

16. The system as claimed in claim 15 additionally comprising:

a first film on the first portion of the transparent substrate having the first resolution enhancement structure therein; and

a second film on the second portion of the transparent substrate having the second resolution enhancement structure therein.

17. The system as claimed in claim 15 additionally comprising:

a first film on the transparent substrate;

a second film on the first film having a portion of the second film removed to form the first resolution enhancement structure in the first film; and

the second resolution enhancement structure in the first and second film.

18. The system as claimed in claim 15 wherein:

the first resolution enhancement structure uses a structure selected from a group consisting of a binary mask portion, a phase shift mask portion, a proximity

effect mask portion, an alternating phase shift mask portion, an attenuated

phase shift mask portion, and a combination thereof.

19. The system as claimed in claim 15 wherein:

the first resolution enhancement structure is over a core portion of the mask; and

the second resolution enhancement structure is over a periphery portion of the mask.

20. The system as claimed in claim 15 wherein:

the mask is in a lithography system.

21. The system as claimed in claim 15 additionally comprising:

a semiconductor substrate having tightly spaced structures on the first portion and isolated structures on the second portion of the semiconductor substrate.

22. A phase controlling semiconductor manufacturing enhancement system comprising:

a light-transparent substrate;

a first resolution enhancement structure over a first portion of the light-transparent substrate; and

a second resolution enhancement structure over a second portion of the light-transparent substrate, the second resolution enhancement structure different from the first resolution enhancement structure, the second resolution enhancement structure has a single partial light-transparent film on the light-transparent substrate and an opaque film on the partially light-transparent film; and

the light-transparent substrate, the first resolution enhancement structure, and the second resolution enhancement structure from a patterned mask.

23. The system as claimed in claim 22 additionally comprising:

an opaque film on the first portion of the light-transparent substrate having the first resolution enhancement structure therein; and

a partially transparent film on the second portion of the light-transparent substrate having the second resolution enhancement structure therein.

24. The system as claimed in claim 22 additionally comprising:

a partially transparent film on the transparent substrate;

an opaque film on the partially transparent film having a portion of the opaque film removed to form the first resolution enhancement structure in the partially transparent film; and

the second resolution enhancement structure in the partially transparent and opaque films.

25. The system as claimed in claim 22 wherein:

the first resolution enhancement structure uses a structure selected from a group consisting of a binary mask portion, a phase shift mask portion, a proximity effect mask portion, an alternating phase shift mask portion, an attenuated phase shift mask portion, and a combination thereof; and

the second resolution enhancement structure uses a structure selected from a group consisting of a binary mask portion, a phase shift mask portion, a proximity effect mask portion, an alternating phase shift mask portion, an attenuated phase shift mask portion, and a combination thereof.

26. The system as claimed in claim 22 wherein:

the first resolution enhancement structure is over a core portion of the mask; and

the second resolution enhancement structure is over a periphery portion of the patterned mask.

27. The system as claimed in claim 22 wherein:

the patterned mask is in a photolithography system.

28. The system as claimed in claim 22 additionally comprising:

a semiconductor substrate having proximally spaced structures on the first portion in a core portion of the semiconductor substrate and distally spaced structures on the second portion in a peripheral portion of the semiconductor substrate.