Vector processing system
View Patent ↗A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.
1. A vector processing system comprising:
a circuit for receiving an instruction defining multiple value pairs, an operation to be executed and a scalar modifier;
a plurality of parallel processing units, each arranged to receive one of said value pairs and to implement the defined operation on said value pair to generate a respective result, wherein each parallel processing unit is identified by an index; and
a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to return the index of one of the plurality of parallel processing units.
2. The vector processing system according to claim 1 , wherein the scalar results unit is operable to generate as a single output value the result received from a predetermined one of said parallel processing units.
3. The vector processing unit according to claim 1 , wherein the scalar results unit is operable to sum the results of die parallel processing units, a single output value being the sum of the results.
4. The vector processing system according to claim 1 , wherein the scalar results unit returns the index of the minimum result.
5. The vector processing system according to claim 1 , wherein the scalar results unit returns the index of the maximum result.
6. The vector processing system according to claim 1 , wherein each parallel processing unit comprises at least one flag, and wherein a selected parallel processing unit is selectable for operation in dependence on a condition defined by said at least one flag, when compared with a condition defined in the instruction to be executed.
7. The vector processing system according to claim 6 , wherein the scalar result unit processes the results only of selected ones of the parallel processing units.
8. The vector processing system according to claim 1 , wherein the system further comprises a vector register file for holding packed operands, each operand comprising multiple values.
9. The vector processing system according to claim 1 , wherein the system further comprises a scalar unit for performing a scalar instruction on a pair of input Values.
10. The vector processing system according to claim 9 , wherein the scalar unit comprises a plurality of scalar registers.
11. The vector processing system according to claim 10 , wherein a single output value of the scalar result unit is supplied to one of said scalar registers as defined by the instruction.
12. A method of vector processing, the method comprising:
supplying a plurality of value pairs to a plurality of parallel processing units;
executing an operation in the parallel processing units, thereby generating a plurality of vector results; and
processing the plurality of vector results according to a scalar modifier to return an index of one of the plurality of parallel processing units.
13. The method according to claim 12 , wherein the method further comprises:
supplying the index value to a scalar register.
14. The method according to claim 12 , wherein vector results associated with an active parallel processing unit an included while processing the plurality of vector results.
15. The method according to claim 12 , wherein the vector results of the parallel processing units are written to a vector register file.
16. The method of claim 12 , wherein the index indicates the location of the minimum vector result.
17. The method of claim 12 , wherein the index indicates the location of the maximum vector result.
18. An integrated circuit for vector processing, wherein the integrated circuit comprises:
a memory having stored thereon a computer program comprising a sequence of instructions including vector instructions, each vector instruction defining
multiple value pairs,
an operation to be executed, and
a scalar modifier; and
a processor for executing the operation on each of said value pairs to generate a plurality of results, wherein the scalar modifier determines how said plurality of results are processed to generate a single output value that is an index of a result in said plurality of results.
19. The integrated circuit of claim 18 , wherein the index indicates the location of the minimum result.
20. The integrated circuit of claim 18 , wherein the index indicates the location of the maximum result.