Granted Patent B2

US 6,996,656 · App. 10/284,994 · Granted Feb 7, 2006

Abstract

Claims (41)

1. A computing system comprising:

at least one adaptive processor;

at least one external peripheral device;

a memory subsystem coupled to the at least one adaptive processor and a memory controller, wherein the memory controller manages memory transactions between the memory subsystem and the at least one external peripheral; and

at least one arbitration port coupled to the memory controller and configured to receive an external arbitration signal from the at least one adaptive processor, wherein the arbitration port in the memory controller enables the external peripheral device and the adaptive processor to share me memory subsystem without the data from the adaptive processor passing through the memory controller.

2. The computing system of claim 1 wherein the arbitration port is implemented in a north bridge component of a system chipset.

3. The computing system of claim 2 further comprising:

a plurality of interface ports implemented by the north bridge component, each of the plurality of interface ports supporting memory transactions from external systems;

an arbitration mechanism within the north bridge component for arbitrating amongst the plurality of interface ports for access to the memory subsystem;

wherein the at least one arbitration port couples to the arbitration mechanism.

4. The computing system of claim 2 further comprising:

a plurality of interface ports implemented by the north bridge component, each of the plurality of interface ports supporting memory transactions from external systems;

an internal arbitration mechanism within the north bridge component for arbitrating amongst the plurality of interface ports for access to the memory subsystem; and

an external arbitration mechanism coupled to provide the arbitration signal over the arbitration port to the internal arbitration mechanism.

5. The computing system of claim 1 wherein the arbitration port is implemented in a memory controller.

6. The computing system of claim 1 wherein the memory controller is integrated with the at least one processor and the arbitration port is implemented in the memory controller of the adaptive processor.

7. The computing system of claim 1 wherein multiple agents access the at least one arbitration port to conduct transactions with the memory subsystem.

8. A computing system comprising:

at least one adaptive processor;

at least one microprocessor;

a memory subsystem;

a memory bus coupled to the at least one adaptive processor, the at least one microprocessor, and the memory subsystem;

a memory and I/O controller for managing random access of the at least one microprocessor to the memory bus;

an arbitration mechanism coupled to the at least one adaptive processor for arbitrating access between the at least one adaptive processor and the memory and I/O controller to the memory bus;

wherein the at least one adaptive processor accesses the memory subsystem via the memory bus through the arbitration mechanism without passing through the memory and I/O controller; and

at least one interface port within the arbitration mechanism operable to enable an external agent to arbitrate for control of the memory subsystem, wherein the arbitration mechanism is implemented externally from the memory and I/O controller.

9. A memory and I/O controller for a computer system comprising:

one or more memory user ports for coupling to devices that generate memory access requests;

a memory bus port coupled to system memory;

an arbitration mechanism operable to grant arbitrated access to the system memory by the devices that generate memory access requests; and

an external arbitration port coupled to the arbitration mechanism, wherein the arbitration mechanism is responsive to a signal on the external arbitration port to grant arbitrated access to the system memory by an external device controlling the external arbitration port, wherein the external device comprises at least one adaptive processor,

wherein the memory and I/O controller interfaces directly with system memory.

10. The memory and I/O controller of claim 9 wherein the arbitration mechanism is implemented within a north bridge component of a system chipset.

11. The memory and I/O controller of claim 10 wherein the external arbitration port comprises a request signal port and a grant signal port.

12. A computing system comprising:

at least one microprocessor;

a memory subsystem;

a SNAP device coupled to the memory subsystem through a memory bus;

a memory controller coupled to the microprocessor and the memory subsystem and operative to manage memory transactions between the memory subsystem and the at least one microprocessor;

at least one arbitration port coupled to the memory controller and to the SNAP device, configured to receive an external arbitration signal; and

a switch having one or more ports coupled to the one or more adaptive processors, the switch operable to selectively couple one of the adaptive processors to the SNAP device.

Assignments (9)