Patent Assignment
Reel/Frame 063723/0139
Release of Security Interest in Specified Patents
Recorded: 2023-05-22
Pages: 49
Assignor
BARINGS FINANCE LLC, AS COLLATERAL AGENT
Executed: 2023-05-01
Assignee
RPX CORPORATION
FOUR EMBARCADERO CENTER, SUITE 4000, SAN FRANCISCO, CALIFORNIA, 94111
Covered Properties
(55)
Fpga Platform as a Service (Paas)
PCT:
PCT/US2017/057274 ↗
Multiprocessor Computer Architecture Incorporting a Plurality of Memory Algorithm Processors in the Memory Subsystem
Patent:
6,076,152 →
Application:
08/992,763 →
System and Method for Dynamic Priority Conflict Resolution in a Multi-Processor Computer System Having Shared Memory Resources
Patent:
6,026,459 →
Application:
09/018,032 →
Split Directory-Based Cache Coherency Technique for a Multi-Processor Computer System
Patent:
6,295,598 →
Application:
09/108,088 →
Multiprocessor Computer Architecture Incorporating a Plurality of Memory Algorithm Processors in the Memory Subsystem
Patent:
6,247,110 →
Application:
09/481,902 →
Multiprocessor with Each Processor Element Accessing Operands in Loaded Input Buffer and Forwarding Results to Fifo Output Buffer
Patent:
6,339,819 →
Application:
09/563,561 →
System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
Patent:
6,356,983 →
Application:
09/624,788 →
System and Method for Semaphore and Atomic Operation Management in a Multiprocessor
Patent:
6,594,736 →
Application:
09/638,365 →
System and Method for Accelerating Web Site Access and Processing Utilizing a Computer System Incorporating Reconfigurable Processors Operating Under a Single Operating System Image
Switch/Network Adapter Port for Clustered Computers Employing a Chain of Multi-Adaptive Processors in a Dual in-Line Memory Module Format
Bandwidth Enhancement for Uncached Devices
Interface for Integrating Reconfigurable Processors into a General Purpose Computing System
Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
Application:
10/142,045 →
Publication:
US 2003/0212853
System and Method for Explict Communication of Messages Between Processes Running on Different Nodes in a Clustered Multiprocessor System
Computer System Architecture and Memory Controller for Close-Coupling Within a Hybrid Processing System Utilizing an Adaptive Processor Interface Port
System and Method for Providing an Arbitrated Memory Bus in a Hybrid Computing System
System and Method for Partitioning Control-Dataflow Graph Representations
Process for Converting Programs in High-Level Programming Languages to a Unified Executable for Hybrid Computing Platforms
Multi-Adaptive Processing Systems and Techniques for Enhancing Parallelism and Performance of Computational Functions
Debugging and Performance Profiling Using Control-Dataflow Graph Representations with Reconfigurable Hardware Emulation
System and Method for Converting Control Flow Graph Representations to Control-Dataflow Graph Representations
Efficiency of Reconfigurable Hardware
Multiprocessor Computer Architecture Incorporating a Plurality of Memory Algorithm Processors in the Memory Subsystem
Switch/Network Adapter Port Coupling a Reconfigurable Processing Element to One or More Microprocessors for Use with Interleaved Memory Controllers
System and method for scalable interconnection of adaptive processor nodes for clustered computer systems
Application:
10/340,400 →
Publication:
US 2004/0139297
Map Compiler Pipelined Loop Structure
Switch/Network Adapter Port Incorporating Shared Memory Resources Selectively Accessible by a Direct Execution Logic Element and One or More Dense Logic Devices
Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
Application:
10/869,199 →
Publication:
US 2004/0236877
System and Method of Enhancing Efficiency and Utilization of Memory Bandwidth in Reconfigurable Hardware
Multiprocessor Computer Architecture Incorporating a Plurality of Memory Algorithm Processors in the Memory Subsystem
Switch/Network Adapter Port for Clustered Computers Employing a Chain of Multi-Adaptive Processors in a Dual in-Line Memory Module Format
Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
Application:
11/119,598 →
Publication:
US 2005/0257029
Interface for Integrating Reconfigurable Processors into a General Purpose Computing System
Switch/Network Adapter Port Coupling a Reconfigurable Processing Element to One or More Microprocessors for Use with Interleaved Memory Controllers
Reconfigurable Processor Element Utilizing Both Coarse and Fine Grained Reconfigurable Elements
Process for Converting Programs in High-Level Programming Languages to a Unified Executable for Hybrid Computing Platforms
Dynamic Priority Conflict Resolution in a Multi-Processor Computer System Having Shared Resources
Elimination of Stream Consumer Loop Overshoot Effects
Multi-Adaptive Processing Systems and Techniques for Enhancing Parallelism and Performance of Computational Functions
Switch/Network Adapter Port Incorporating Shared Memory Resources Selectively Accessible by a Direct Execution Logic Element and One or More Dense Logic Devices in a Fully Buffered Dual in-Line Memory Module Format (Fb-Dimm)
Heterogeneous Computing System Comprising a Switch/Network Adapter Port Interface Utilizing Load-Reduced Dual in-Line Memory Modules (Lr-Dimms) Incorporating Isolation Memory Buffers
Application:
13/286,996 →
Publication:
US 2012/0117318
System and Method for Computational Unification of Heterogeneous Implicit and Explicit Processing Elements
Mobile Electronic Devices Utilizing Reconfigurable Processing Techniques to Enable Higher Speed Applications with Lowered Power Consumption
Application:
13/365,090 →
Publication:
US 2013/0157639
Multi-Processor Computer Architecture Incorporating Distributed Multi-Ported Common Memory Modules
System and Method for Computational Unification of Heterogeneous Implicit and Explicit Processing Elements
System and Method for Thermally Coupling Memory Devices to a Memory Controller in a Computer Memory Board
System and Method for Retaining Dram Data When Reprogramming Reconfigurable Devices with Dram Memory Controllers
Patent:
9,153,311 →
Application:
14/288,094 →
System and Method for Retaining Dram Data When Reprogramming Reconfigurable Devices with Dram Memory Controllers Incorporating a Data Maintenance Block Colocated with a Memory Module or Subsystem
System and Method for Retaining Dram Data When Reprogramming Reconfigurable Devices with Dram Memory Controllers Incorporating a Data Maintenance Block Colocated with a Memory Module or Subsystem
Fpga Platform as a Service (Paas)
Application:
16/343,401 →
Publication:
US 2019/0250941
System and Method for Retaining Dram Data When Reprogramming Reconfigureable Devices with Dram Memory Controllers Incorporating a Data Maintenance Block
Fpga Based Data and Currency Exchange
Application:
16/938,903 →
Publication:
US 2020/0356963
Application Logic Architecture Defining Separate Processing Planes
Application:
17/218,128 →
Publication:
US 2021/0303315
Secure Heterogenous Computing Platform
Application:
17/218,132 →
Publication:
US 2021/0303723
Snap Interface Using Memory Buffers
Application:
61/410,676 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Sep 23, 2013
From: SRC COMPUTERS, LLC
To: FREEMAN CAPITAL PARTNERS LP
Reel/Frame 031263/0288 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0900 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0894 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0865 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0859 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0805 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0769 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0566 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0592 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0660 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0678 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0691 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0712 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0736 →
Merger
Oct 30, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031514/0718 →
Merger
Oct 31, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031523/0088 →
Merger
Oct 31, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031522/0872 →
Merger
Oct 31, 2013
From: SRC COMPUTERS, INC.
To: SRC COMPUTERS, LLC
Reel/Frame 031523/0041 →
Release of Security Interest
Feb 11, 2016
From: FREEMAN CAPITAL PARTNERS LP
To: SRC COMPUTERS, LLC
Reel/Frame 037707/0196 →
Assignment of Assignor's Interest
Feb 13, 2016
From: SRC COMPUTERS, LLC
To: SRC LABS, LLC
Reel/Frame 037820/0147 →
Assignment of Assignor's Interest
Aug 2, 2017
From: SRC LABS, LLC
To: SAINT REGIS MOHAWK TRIBE
Reel/Frame 043174/0318 →
Assignment of Assignor's Interest
Apr 17, 2019
From: ROOKE, TODD A.; WILKINSON, TIMOTHY P.
To: SRC LABS, LLC
Reel/Frame 048915/0097 →
Assignment of Assignor's Interest
May 22, 2019
From: SAINT REGIS MOHAWK TRIBE
To: DIRECTSTREAM, LLC
Reel/Frame 049251/0855 →
Assignment of Assignor's Interest
Jan 24, 2020
From: DIRECTSTREAM LLC
To: FG SRC LLC
Reel/Frame 051615/0344 →
Patent Security Agreement
May 1, 2023
From: RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 063503/0742 →