Map compiler pipelined loop structure
View Patent ↗A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.
1. A reconfigurable computer system including control-flow dataflow pipelined loop structures, the system comprising:
a multi-adaptive processor, wherein the multi-adaptive processor includes field programmable gate arrays; and
a multi-adaptive processor compiler capable of creating code executable on the multi-adaptive processor, wherein the multi-adaptive processor compiler creates code forming a pipelined loop structure, the pipelined loop structure comprising;
a loop body that processes an input value to generate an output value in successive iterations of the loop body, wherein the output value is captured by a circulate node coupled to the loop body;
a loop valid node coupled to the loop body that determines a final loop iteration; and
an output value storage node coupled to the circulate node, wherein the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred preserving a final loop value based on the final loop iteration.
2. The pipelined loop structure of claim 1 , wherein the loop valid node outputs a loop-valid termination signal upon determining the final loop iteration has occurred.
3. The pipelined loop structure of claim 2 , wherein the loop valid node outputs the loop-valid termination signal for every loop iteration after the final loop iteration has occurred, until the loop is reinitiated.
4. The pipelined loop structure of claim 2 , wherein the loop-valid termination signal comprises a data bit.
5. The pipelined loop structure of claim 1 , comprising a termination node copied to the loop valid node and the output value storage node.
6. The pipelined loop structure of claim 5 , wherein the termination node comprises a termination input to receive the loop-valid termination signal from the loop valid node.
7. The pipelined loop structure of claim 6 , wherein the termination node comprises a termination output to send a storage node termination signal to the output value storage node.
8. The pipelined loop structure of claim 1 , wherein the pipelined loop structure comprises a loop driver node coupled to the circulate node, wherein the loop driver node sets a period for each iteration of the loop body.
9. The pipelined loop structure of claim 8 , wherein clock latency is based on a period value that is input into the loop driver node.
10. A reconfigurable computer system including a multi-adaptive processor and a multi-adaptive compiler, the multi-adaptive compiler capable of converting high level instructions into code executable in the multi-adaptive processor, including instructions for forming a control-flow dataflow pipelined loop structure, the pipelined structure comprising:
a loop body that processes a first input value to generate an output value in successive iterations of the loop body, wherein the output value is captured by a circulate node coupled to the loop body; and
a loop driver node coupled to the circulate node, wherein the loop driver node sets a period for each iteration of the loop body such that one or more clock cycles pass before the loop body processes a second input value, and wherein the loop drive node outputs signals related to stateful functional units.
11. The pipelined loop structure of claim 10 , wherein the loop driver node outputs a CIRC_TRIGGER signal to tell the circulate node that a loop is starting.
12. The pipelined loop structure of claim 10 , wherein the loop driver node outputs a START signal to trigger the start of a loop.
13. The pipelined loop structure of claim 10 , wherein the loop driver node outputs a LOOP—STARTING signal to clear the state of a node that requires a reset pulse.
14. The pipelined loop structure of claim 10 , wherein the loop driver node outputs a LEADING signal to tell a periodic-input node to load a value.
15. The pipelined loop structure of claim 10 , wherein the period value equals the period of the longest loop-carried scalar cycle in the pipelined loop structure.
16. The pipelined loop structure of claim 10 , wherein the period is based on a period value that is input into the loop driver node.
17. The pipelined loop structure of claim 10 , comprising a loop valid node coupled to the loop body that determines a final loop iteration.
18. The pipelined loop structure of claim 17 , wherein the loop valid node outputs a loop-valid termination signal upon determining the final loop iteration has occurred.
19. The pipelined loop structure of claim 18 ,comprising an output value storage node coupled to the circulate node.
20. The pipelined loop structure of claim 19 , wherein the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred.
21. The pipelined loop structure of claim 20 , comprising a termination node coupled to the loop valid node and the output value storage node.