Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
View Patent ↗A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.
1. A method of converting high-level language source code into a unified executable comprising:
generating an object file from a reconfigurable hardware portion of the high-level language source code; and
integrating the object file into the unified executable.
2. The method of claim 1 , wherein said method comprises converting the high-level language source code into a control flow graph representation.
3. The method of claim 2 , wherein said method comprises converting the control flow graph representation into a control-data flow graph representation.
4. The method of claim 3 , wherein said method comprises partitioning the control-flow data graph into a instruction processor portion and the reconfigurable hardware portion.
5. The method of claim 1 , wherein said method comprises converting the reconfigurable hardware portion into a hardware definition language file.
6. The method of claim 5 , wherein said method comprises converting the hardware definition language file into a reconfigurable hardware bitstream file.
7. The method of claim 6 , wherein said method comprises converting the reconfigurable hardware bitstream file into the object file.
8. A method of forming a unified executable comprising:
converting a high level language source code into a control flow graph representation;
converting the control flow graph representation into a control-data flow graph representation;
partitioning the control-data flow graph into a instruction processor portion and a reconfigurable hardware portion;
converting the reconfigurable hardware portion of the control-data flow graph into a hardware definition language portion and the instruction processor portion into a instruction processor object file;
converting the hardware definition language portion into a reconfigurable hardware bitstream;
converting the reconfigurable hardware bitstream into a bitstream object file that is readable by a instruction processor; and
integrating the bitstream object file with the instruction processor object file to form the unified executable.
9. A system for forming a unified executable comprising:
a partitioner to partition control-dataflow graph data into a reconfigurable hardware portion and a instruction processor portion; and
a high-level language converter to convert a high-level language into control flow graph representations.
10. The system of claim 9 , wherein said system comprises a control flow graph to control-dataflow graph converter to convert the control flow graph representations into the control-dataflow graph data.
11. The system of claim 9 , wherein said system comprises a control-dataflow graph to hardware definition language converter to convert the reconfigurable hardware portion of the control-dataflow graph data to a hardware definition language file.
12. The system of claim 11 , wherein said system comprises a hardware definition language to bitstream converter to convert the hardware definition language file to a bitstream file.
13. The system of claim 12 , wherein said system comprises a bitstream to object file converter to convert the bitstream file into a bitstream object file.
14. The system of claim 13 , wherein said system comprises a linker to integrate the bitstream object file into the unified executable.
15. The system of claim 9 , wherein said system comprises a support hardware logic module.
16. The system of claim 9 , wherein said system comprises a user hardware logic module.
17. The system of claim 9 , wherein said system comprises a runtime library.
18. The system of claim 9 , wherein said system comprises a hybrid computer comprising a instruction processor and reconfigurable hardware.
19. The system of claim 18 , wherein said reconfigurable hardware comprises a multi-adaptive processor (MAP).
20. A system for forming a unified executable that is executable on a hybrid reconfigurable hardware-instruction processor computer, said system comprising:
a high-level language converter to convert a high-level language into control flow graph representations;
a control flow graph to control-dataflow graph converter to convert the control flow graph representations into control-dataflow graph representations;
a partitioner to partition the control-dataflow graph representations into a reconfigurable hardware portion and a instruction processor portion;
a control-dataflow graph to hardware definition language converter to convert the reconfigurable hardware portion of the control-dataflow graph representations to a hardware definition language file;
a hardware definition language to bitstream converter to convert the hardware definition language file to a bitstream file;
a bitstream to object file converter to convert the bitstream file into a bitstream object file; and
a linker to integrate the bitstream object file into the unified executable.
21. A computer program product comprising:
a computer usable medium having computer readable program code embodied therein for causing a formation of a unified executable, the computer readable program code comprising:
computer readable program code for causing a computer to convert a high level language source code into a control flow graph representation;
computer readable program code for causing the computer to convert the control flow graph into a control-data flow graph;
computer readable program code for causing the computer to partition the control-data flow graph into a instruction processor portion and a reconfigurable hardware portion;
computer readable program code for causing the computer to convert the reconfigurable hardware portion of the control-data flow graph into a hardware definition language portion and the instruction processor portion into a instruction processor object file;
computer readable program code for causing the computer to convert the hardware definition language portion into a reconfigurable hardware bitstream;
computer readable program code for causing the computer to convert the reconfigurable hardware bitstream into a bitstream object file that is readable by a instruction processor; and
computer readable program code for causing the computer to integrate the bitstream object file with the instruction processor object file to form the unified executable.