Granted Patent B2

US 6,941,539 · App. 10/285,401 · Granted Sep 6, 2005

Abstract

Claims (34)

1. A method of computing a function array in reconfigurable hardware comprising:

forming in the reconfigurable hardware, a first delay queue and a second delay queue;

inputting from a source array outside the reconfigurable hardware, a first value into the first delay queue and a second value into the second delay queue;

defining in the reconfigurable hardware, a window array comprising a first cell and a second cell;

inputting the first value from the first delay queue into the first cell and the second value from the second delay queue into the second cell; and

calculating an output value for the function array based on the window array.

2. The method of claim 1 , wherein the first value and the second value of the source array are input into the reconfigurable hardware just once to compute the function array.

3. The method of claim 1 , wherein the reconfigurable hardware comprises a field programmable gate array (FPGA).

4. The method of claim 1 , wherein the source array is a two dimensional array.

5. The method of claim 1 , wherein the function array is a two dimensional array.

6. The method of claim 5 , wherein the function array is a median filter output array for image processing.

7. The method of claim 1 , wherein the function array describes hydrodynamic behavior in a fluid system.

8. The method of claim 1 , wherein the window array is a two dimensional array.

9. The method of claim 8 , wherein the window array has dimensions of equal length.

10. The method of claim 1 , wherein the first delay queue and the second delay queue comprise FIFO buffers.

11. The method of claim 1 , wherein said method further comprises:

determining whether the output value is a junk value, wherein the output value is stored in a result array unless it is the junk value.

12. A method of loop stripmining comprising:

forming in reconfigurable hardware, a first delay queue with a first length equal to a maximum number of values stored in the delay queue;

forming first a sub-array from a first portion of a source array, wherein at least one dimension of the sub-array has a size equal to the first length of the first delay queue;

loading values from the first sub-array into the first delay queue; and

stepping the sub-array to a second portion of the source array.

13. The method of claim 12 , wherein the reconfigurable hardware comprises a field programmable gate array (FPGA).

14. The method of claim 12 , wherein the source array is a two-dimensional array having a depth and a width.

15. The method of claim 14 , wherein the sub-array spans the width of the source array.

16. The method of claim 12 , wherein the first portion and the second portion of the source array overlap by at least one row of the source array.

17. The method of claim 12 , wherein said method further comprises forming in the reconfigurable hardware a second delay queue with a second length equal to the first length of the first delay queue.

18. The method of claim 17 , wherein said method further comprises loading the values from the first delay queue into the second delay queue.

19. A method of calculating output values in a fused producer/consumer loop structure comprising:

forming in a reconfigurable hardware, a first delay queue and a second delay queue;

loading a first output value from a producer function into the first delay queue;

loading a second output value from the producer function and loading into the first delay queue, wherein the first output value is loaded into the second delay queue; and

inputting the first output value from the second delay queue, the second output value from the first delay queue, and a third output value from the producer function into a consumer function to calculate a consumer output value.

20. The method of claim 19 , wherein the reconfigurable hardware comprises a field programmable gate array (FPGA).

Assignments (9)