Display controller
Systems and methods are disclosed for controlling a display device having a display scan line rate by storing incoming data in a buffer, the buffer having a usage level measure; comparing the usage level to the display scan line rate; and adjusting a width of a display scan line to avoid buffer overflow or underflow. The system avoids a costly external frame buffer and automatically handles uncertainties such as jitter in input and output clocks when the system operates in different environments.
1. A method for controlling a display device having a scan line rate, comprising:
storing incoming data in a buffer, the buffer having a usage level measure;
comparing the usage level to the scan line rate;
generating a first control signal configured to contract the period of a horizontal sync (HSYNC) signal in response to said usage level exceeding a first predetermined threshold;
generating a second control signal configured to lengthen the period of said horizontal sync (HSYNC) signal in response to said usage level falling below a second predetermined threshold;
generating a third control signal configured to set a default period of said horizontal sync (HSYNC) signal;
multiplexing said first control signal, said second control signal and said third control signal to generate a request signal; and
adjusting a period of said horizontal sync (HSYNC) signal in response to said request signal to avoid buffer overflow or underflow.
2. The method of claim 1 , further comprising snooping the usage level of the buffer.
3. The method of claim 1 , further comprising automatically performing scaling up or scaling down an image.
4. The method of claim 1 , further comprising performing interpolation or decimation on an image.
5. The method of claim 4 , wherein the performing interpolation or decimation further comprises determining image diagonal characteristics.
6. The method of claim 5 , further comprising reading multiple vertical pixels simultaneously.
7. The method of claim 6 , further comprising performing two-dimensional image filtering operations on the multiple vertical pixels.
8. The method of claim 5 , wherein the storing further comprises forming a First In First Out (FIFO) ring buffer.
9. The method of claim 1 , further comprising performing post-processing on video data going to the display device.
10. The method of claim 9 , wherein the post-processing further comprises adjusting contrast, adjusting brightness, adjusting hue and saturation, reducing noise, performing gamma correction, or enhancing a video image.
11. The method according to claim 1 , wherein:
generating first control signal comprises the steps of (i) determining a difference between a write pointer of the buffer and a read pointer of the buffer, (ii) determining a first number of clock cycles by which the difference between the write pointer and the read pointer exceeds the first predetermined threshold by subtracting the first predetermined threshold from the difference between the write pointer and the read pointer and (iii) adding the first number of clock cycles to the default period of the horizontal sync (HSYNC) signal; and
generating said second control signal comprises (i) determining the difference between the write pointer of the buffer and the read pointer of the buffer, (ii) determining a second number of clock cycles by which the difference between the write pointer and the read pointer falls below the second predetermined threshold by subtracting the second predetermined threshold from the difference between the write pointer and the read pointer and (iii) subtracting the second number of clock cycles from the default period of the horizontal sync (HSYNC) signal, wherein the default period of the horizontal sync (HSYNC) signal is expressed as a number of clock cycles.
12. The method according to claim 11 , further comprising:
limiting the first number of clock cycles to a value equal to or less than a first predetermined limit value; and
limiting the second number of clock cycles to a value equal to or less than a second predetermined limit value.
13. The method according to claim 12 , wherein the first predetermined threshold, the second predetermined threshold, the first predetermined limit value and the second predetermined limit value are programmable.
14. A controller for a digital display, comprising:
a buffer to receive image data, the buffer having a usage level measure;
a timing controller to drive the display having a scan line rate; and
a buffer controller coupled to the buffer and the timing controller, the buffer controller snooping the usage level of the buffer, comparing the usage level to the scan line rate, and adjusting a horizontal sync (HSYNC) signal to avoid buffer overflow or underflow, wherein said buffer controller is further configured (i) to generate a first control signal configured to contract the period of said horizontal sync (HSYNC) signal in response to said usage level exceeding a first predetermined threshold, (ii) to generate a second control signal configured to lengthen the period of said horizontal sync (HSYNC) signal in response to said usage level falling below a second predetermined threshold, (iii) to generate a third control signal configured to set a default period of said horizontal sync (HSYNC) signal and (iv) to multiplex said first control signal, said second control signal, and said third control signal to generate a horizontal sync request signal.
15. The controller of claim 14 , further comprising an interpolation decimation engine coupled to the buffer, the interpolation decimation engine minimizing diagonal image jaggedness.
16. The controller of claim 15 , further comprising a post-processing circuit coupled to the interpolation decimation engine and the timing controller.
17. The controller of claim 14 , wherein the digital display is one of liquid crystal displays, plasma displays and progressive-scan televisions.
18. The controller of claim 14 , wherein the buffer controller receives at least two lines of display and processes the lines at same time.
19. The controller of claim 14 , wherein the buffer controller performs interpolation or decimation on an image.
20. The controller of claim 19 , wherein the buffer controller further analyzes image diagonal characteristics.
21. The controller of claim 14 , wherein the buffer controller changes a line width to adjust the line rate.
22. A method for controlling a liquid crystal display (LCD) panel with an LCD horizontal sync (HSYNC) signal, comprising:
storing incoming data in a buffer according to a first clock and retrieving outgoing data from the buffer according to a second clock, the buffer having a usage level measure;
comparing the usage level to a range determined by a first predetermined threshold and a second predetermined threshold;
generating a horizontal sync request signal in response to (i) a first control signal configured to contract a period of the HSYNC signal by a first number of cycles of the second clock by which the usage level is above the first predetermined threshold, (ii) a second control signal configured to lengthen the period of the HSYNC signal by a second number of cycles of the second clock by which the usage level is below the second predetermined threshold and (iii) a third control signal configured to set a default period of the HSYNC signal to a predetermined number of cycles of the second clock when the usage level is in the range between the first predetermined threshold and the second predetermined threshold; and
adjusting a period of the HSYNC signal in response to the horizontal sync request signal.
23. A liquid crystal display (LCD) controller, comprising:
a buffer configured to receive image data according to a first clock and present image data according to a second clock, the buffer having a usage level measure;
an interpolation/decimation engine coupled to the buffer, the interpolation/decimation engine minimizing diagonal image jaggedness;
a timing controller coupled to the interpolation/decimation engine;
a buffer controller coupled to the buffer, the interpolation/decimation engine and the timing controller, the buffer controller (a) snooping the usage level of the buffer, (b) comparing the usage level to a range determined by a first predetermined threshold and a second predetermined threshold, (c) generating a horizontal sync request signal in response to (i) a first control signal configured to contract a period of a LCD horizontal sync (HSYNC) signal by a first number of cycles of the second clock by which the usage level is above the first predetermined threshold, (ii) a second control signal configured to lengthen the period of said LCD horizontal sync (HSYNC) signal by a second number of cycles of the second clock by which the usage level is below the second predetermined threshold, and (iii) a third control signal configured to set a default period of said horizontal sync (HSYNC) signal to a predetermined number of cycles of the second clock when the usage level is in the range between the first predetermined threshold and the second predetermined threshold and (d) adjusting the period of said LCD horizontal sync (HSYNC) signal in response to said horizontal sync request signal; and
a post-processing circuit coupled to the interpolation/decimation engine and the timing controller.