Low-energy writing in cross-point array memory devices
View Patent ↗Disclosed are improved cross-point array memory devices. In one embodiment, a memory device comprises a cross-point array of memory cells, each memory cell including a storage element and a current concentrating feature that concentrates current applied to the storage element. In another embodiment, a memory device comprises a cross-point array of memory cells, each memory cell including a storage element having a preprogrammed filament fuse configured to be disabled during a write procedure.
1. A memory device, comprising:
a cross-point array of memory cells, each memory cell comprising:
a storage element; and
a current concentrating feature that concentrates current applied to the storage element.
2. The memory device of claim 1 , further comprising a control element and an intermediate conductor positioned between the control element and the storage element.
3. The memory device of claim 2 , wherein the control element comprises a tunnel junction device.
4. The memory device of claim 2 , wherein the control element comprises a diode.
5. The memory device of claim 2 , wherein the storage element comprises an anti-fuse element.
6. The memory device of claim 2 , wherein the storage element comprises a phase-change element.
7. The memory device of claim 6 , wherein the current concentrating feature comprises a protrusion that extends from the intermediate conductor to the storage element.
8. The memory device of claim 7 , wherein the protrusion comprises a sharp tip that concentrates current.
9. The memory device of claim 7 , further comprising a layer of insulative material formed on the intermediate conductor such that only a tip of the protrusion contacts the storage element.
10. The memory device of claim 2 , wherein the current concentrating feature comprises a conductive path that has been preprogrammed into a portion of the storage element.
11. The memory device of claim 10 , wherein the conductive path is formed through a first layer of the storage element adjacent the intermediate conductor.
12. The memory device of claim 11 , wherein the storage element further comprises a second layer formed of a state-changing material.
13. The memory device of claim 12 , further comprising a barrier layer that separates the first layer and the second layer of the storage element.
14. The memory device of claim 12 , wherein the first layer is formed of a state-changing material that changes state with lower applied currents than does the state-changing material of the second layer.
15. A process for writing to a memory cell of a memory device, comprising:
applying current to a storage element of the memory cell using a protrusion of an intermediate conductor of the memory cell such that current is concentrated on a relatively small portion of the storage element so as to reduce the amount of energy necessary to change a resistance state of the storage element.
16. A process for facilitating writing to a memory cell of a memory device, comprising:
preprogramming a storage element of the memory cell by forming a current path through a portion of the storage element that concentrates current applied to the storage element so as to reduce the amount of energy necessary to change a resistance state of the storage element.
17. A memory device, comprising:
a cross-point array of memory cells, each memory cell comprising:
a storage element having a preprogrammed filament fuse configured to be disabled during a write procedure.
18. The memory device of claim 17 , further comprising a control element and an intermediate conductor positioned between the control element and the storage element.
19. The memory device of claim 18 , wherein the control element comprises a tunnel junction device.
20. The memory device of claim 18 wherein the control element comprises a diode.
21. The memory device of claim 18 , wherein the storage element comprises an anti-fuse element.
22. A process for writing to a memory cell of a memory device, comprising:
applying a potential to the memory cell of sufficient magnitude to disable a preprogrammed filament fuse formed in a storage element of the memory cell.
23. A memory carrier, comprising:
a carrier;
a mechanical interface connected to the carrier;
at least one memory integrated circuit, the memory integrated circuit comprising a cross-point array of memory cells, each memory cell comprising:
a storage element; and
a current concentrating feature that concentrates current applied to the storage element.
24. The memory carrier of claim 23 , wherein the current concentrating feature comprises a protrusion that extends from the intermediate conductor to the storage element.
25. The memory carrier of claim 23 , wherein the current concentrating feature comprises a conductive path that has been preprogrammed into a portion of the storage element.
26. A memory carrier, comprising:
a carrier;
a mechanical interface connected to the carrier;
at least one memory integrated circuit, the integrated circuit comprising a cross-point array of memory cells, each memory cell comprising:
a storage element a storage element having a preprogrammed filament fuse configured to be disabled during a write procedure.
27. The memory carrier of claim 26 , wherein the storage element comprises an anti-fuse element.
28. An electronic device, comprising:
a microprocessor;
a storage device including a cross-point array of memory cells, each memory cell comprising:
a storage element; and
a current concentrating feature that concentrates current applied to the storage element.
29. The electronic device of claim 28 , wherein the current concentrating feature comprises a protrusion that extends from the intermediate conductor to the storage element.
30. The electronic device of claim 28 , wherein the current concentrating feature comprises a conductive path that has been preprogrammed into a portion of the storage element.
31. An electronic device, comprising:
a microprocessor;
a storage device including a cross-point array of memory cells, each memory cell comprising:
a storage element a storage element having a preprogrammed filament fuse configured to be disabled during a write procedure.
32. The electronic device of claim 31 , wherein the storage element comprises an anti-fuse element.
33. An embedded cubic memory array, comprising:
a package;
a microprocessor; and
memory including a cross-point array of memory cells, each memory cell comprising:
a storage element; and
a current concentrating feature that concentrates current applied to the storage element.
34. The embedded cubic memory array of claim 33 , wherein the current concentrating feature comprises a protrusion that extends from the intermediate conductor to the storage element.
35. The embedded cubic memory array of claim 33 , wherein the current concentrating feature comprises a conductive path that has been preprogrammed into a portion of the storage element.
36. An embedded cubic memory array, comprising:
a package;
a microprocessor; and
memory including a cross-point array of memory cells, each memory cell comprising:
a storage element a storage element having a preprogrammed filament fuse configured to be disabled during a write procedure.
37. The embedded cubic memory array of claim 36 , wherein the storage element comprises an anti-fuse element.