Memory system

1. A memory system comprising:

a memory controller;

a clock generator, connected to said memory controller through a first clock signal line, for propagating a clock signal along said first clock signal line toward said memory controller;

a plurality of second clock signal lines extended to be parallel and adjacent respectively to said first clock signal line, one end of said plurality of second clock signal lines being connected to terminating resistance respectively so that, when the clock signal is propagated along said first clock signal line, a crosstalk signal is propagated along said plurality of second clock signal lines in a direction opposite to the propagation direction of said clock signal;

a plurality of memory modules connected to the other ends of said plurality of second clock signal lines;

a data wired line which is provided for each of said plurality of memory modules and on which a data signal is transmitted between the corresponding memory module to which said data wired line is connected and said memory controller, said data wired line having substantially the same length as that of a portion of said first and second clock signal lines formed between said corresponding memory module and said memory controller; and

a signal line which is provided for each of said plurality of memory modules and by which said corresponding memory module is connected to said memory controller, said signal line having substantially the same length as that of said data wired line;

wherein said memory controller comprises

(i) a location detection circuit which transmits, prior to performing write access to said plurality of memory modules, a location detection signal to the memory module to which write access is performed through said signal line and receives a reflected signal from said memory module, thereby measuring a physical quantity corresponding to a signal propagation time between said memory module and said memory controller; and

(ii) an adjustment circuit which controls timing, at which the data signal is transmitted from said memory controller to said memory module through said data wired line, according to the physical quantity so as to eliminate a phase difference in propagation delay times caused by the length of said data wired line.

2. A memory system comprising:

a memory controller;

a clock generator, connected to said memory controller, for propagating a clock signal on a clock signal line between said memory controller and said clock generator,

one ends of said plurality of signal lines being connected to terminating resistances respectively so that. when the clock signal is propagated along said clock signal line, a crosstalk signal is propagated along said signal line in a direction opposite to the propagation direction of said clock signal; and

a plurality of memory modules connected to the other ends of said plurality of signal lines;

wherein said memory controller comprises

(i) a transmission circuit for transmitting, prior to write access to one of the memory modules, a location detection signal to said memory module, a reflected-signal detection circuit connected at its input to an output of said transmission circuit for measuring a physical quantity corresponding to a signal propagation time between said memory module and memory controller; and

(ii) an adjustment circuit for controlling timing of transmission of the write data according to said physical quantity so as to eliminate a phase difference in propagation delay times caused by the length of the wired line to said memory module for write access to said memory module; and

wherein said adjustment circuit controls the timing of transmission of the write data according to values obtained by calculating said physical quantity, propagation delay time corresponding to a distance between an input of a memory device in said memory module and a connection point between said memory module and said data wired line, and a required signal time between clock and data terminals prescribed by specifications of said memory device.

3. A memory system as set forth in claim 2 , wherein said memory module has a clock stabilization circuit for accepting said clock signal and a reference signal and a memory device having a clock input terminal connected to said clock stabilization circuit, said memory device has a data terminal connected to said data wired line, an output of said clock stabilization circuit is again input thereto as said reference signal via a delay circuit providing a delay time determined by the specifications of said memory module.

4. A memory system as set forth in claim 3 , wherein said adjustment circuit controls the timing of transmission of the write data according to values obtained by calculating said physical quantity and a required signal time between the clock and data terminals prescribed by the specifications of said memory device.

5. A memory system as set forth in claim 2 , wherein said memory controller obtains a residue of an MOD operation over a value corresponding to a multiplication of said calculated values by 1 on the basis of a period TCK of an internal clock of said memory controller for said control of the write data transmission timing.

6. A memory system as set forth in claim 2 , wherein said transmission circuit has substantially the same impedance as that of a signal path for transmission of said location detection signal to said memory module, and said reflected-signal detection circuit has a receiver having a hysteresis characteristic.

7. A memory system as set forth in claim 2 , wherein said adjustment circuit controls timing of transmission of said write data by vertically connecting delay circuit elements corresponding in number to said physical quantity measured by said reflected-signal detection circuit.