Apparatus for synchronizing clock and data between two domains having unknown but coherent phase
View Patent ↗A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse. A synchronizer jitter lockout circuit inputs the edge pulse and the sampling clock and outputs a data sampling enable signal which never coincides with a data transition.
1. A data synchronizer comprising:
a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse; and
a synchronizer jitter lockout circuit inputting the edge pulse and the sampling clock, wherein the synchronizer jitter lockout circuit further includes a register latching an external lock signal and the edge pulse, and outputting an ENGAGED signal,
wherein the synchronizer jitter lockout circuit outputs a data sampling enable signal which never coincides with a data transition.
2. The data synchronizer of claim 1 , wherein the counter is triggered by a LOAD signal generated from ANDing the edge pulse and the ENGAGED signal.
3. The data synchronizer of claim 2 , wherein the synchronizer jitter lockout circuit includes a counter triggered by the edge pulse, wherein the counter is reset by the LOAD signal.
4. A data synchronizer for synchronizing data across two different clock domains, comprising:
a synchronizer inputting a sampling clock and a data clock, and outputting a sync pulse; and
a synchronous clock enabler inputting the sync pulse and the sampling clock, wherein the synchronous clock enabler further includes a register latching an external lock signal and the sync pulse, and outputting an ENGAGED signal,
wherein the synchronous clock enabler ensures that data is never sampled when a metastable condition can occur.
5. The data synchronizer of claim 4 , wherein a counter, triggered by the sync pulse, is triggered by a LOAD signal generated from ANDing the sync pulse and the ENGAGED signal.
6. The data synchronizer of claim 5 , wherein the counter is reset by the LOAD signal.
7. A data synchronizer comprising:
a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse; and
a synchronizer jitter lockout circuit inputting the edge pulse and the sampling clock
wherein the synchronizer jitter lockout circuit includes a counter triggered by the edge pulse, and
wherein the synchronizer jitter lockout circuit outputs a data sampling enable signal.
8. The data synchronizer of claim 7 , wherein the synchronizer jitter lockout circuit further includes a register latching an external lock signal and the edge pulse, and outputting an ENGAGED signal.
9. The data synchronizer of claim 8 , wherein the counter is triggered by a LOAD signal generated from ANDing the edge pulse and the ENGAGED signal.
10. The data synchronizer of claim 9 , wherein the counter is reset by the LOAD signal.
11. A data synchronizer comprising:
a synchronizer inputting a sampling clock and a data clock, and outputting a sync pulse; and
a synchronous clock enabler inputting the sync pulse and the sampling clock,
wherein the synchronous clock enabler includes a counter triggered by the sync pulse, and
wherein the synchronous clock enabler ensures that data is never sampled when a metastable condition can occur.
12. The data synchronizer of claim 11 , wherein the synchronous clock enabler further includes a register latching an external lock signal and the sync pulse, and outputting an ENGAGED signal.
13. The data synchronizer of claim 12 , wherein a counter, triggered by the sync pulse, is triggered by a LOAD signal generated from ANDing the sync pulse and the ENGAGED signal.
14. The data synchronizer of claim 13 , wherein the counter is reset by the LOAD signal.
15. A data synchronizer comprising:
a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse; and
a synchronizer jitter lockout circuit inputting the edge pulse and the sampling clock,
wherein the synchronizer jitter lockout circuit outputs a data sampling enable signal which never coincides with a data transition, and
wherein once a particular edge pulse is selected, subsequent edge pulses are ignored by the synchronizer jitter lockout circuit.
16. A data synchronizer for synchronizing data across two different clock domains, comprising:
a synchronizer inputting a sampling clock and a data clock, and outputting a sync pulse,
wherein once a particular sync pulse is selected, subsequent sync pulses are ignored by the synchronous clock enabler; and
a synchronous clock enabler inputting the sync pulse and the sampling clock,
wherein the synchronous clock enabler ensures that data is never sampled when a metastable condition can occur.