IP Library › Granted Patent US 7,147,710
Granted Patent B2
US 7,147,710 · App. 10/298,740 · Granted Dec 12, 2006

Method of manufacturing epitaxial silicon wafer

Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,147,710
App. No.
10/298,740
Granted
Dec 12, 2006
Kind
B2
Abstract

There is described a method which enables stable manufacture of a high-quality, ultra-thin epitaxial silicon wafer, as well as an epitaxial silicon wafer capable of bearing shipment manufactured by the method. A method of manufacturing an epitaxial silicon wafer having an ultra-thin epitaxial film, by means of forming an epitaxial film on a silicon wafer after having annealed the silicon wafer, includes the steps of: sufficiently smoothing COPs formed in the surface of the silicon wafer by means of appropriately setting annealing conditions according to an size of COPs in the vicinity of a surface of the silicon wafer; and forming an epitaxial film through epitaxial growth.

Claims (38)

1. A method of manufacturing an epitaxial silicon wafer, comprising:

a silicon ingot manufacturing step of pulling a silicon ingot under a pulling condition in which an LSTD density assumes a value of 1×10 6 defects/cm 3 or more so as to obtain shallow recessed pits on a surface of a silicon wafer, when the silicon ingot is manufactured by Czochralski technique;

a step of slicing a silicon wafer off the silicon ingot manufactured in the silicon ingot manufacturing step to obtain the silicon wafer having the shallow recessed pits on the surface of the silicon wafer;

an annealing step for smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is 1000° C. or more; whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped, shallow and wider recesses; and

an epitaxial layer growing step of growing an epitaxial layer on the surface of the smoothed silicon wafer, the grown epitaxial layer being an extremely thin film having a thickness sufficient for causing LPDs on a surface of the grown epitaxial layer to be extinct.

2. A method of manufacturing an epitaxial silicon wafer, comprising:

a silicon ingot manufacturing step of pulling a silicon ingot under a pulling condition in which a COP size becomes 130 nm or less or a perfect crystal so as to obtain shallow recessed pits on a surface of a silicon wafer, when the silicon ingot is manufactured by Czochralski technique;

a step of slicing a silicon wafer off the silicon ingot manufactured in the ingot manufacturing step to obtain the silicon wafer having the shallow recessed pits on the surface of the silicon wafer;

an annealing step for smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is 1000° C. or more, whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped, shallow and wider recesses; and

an epitaxial layer growing step of growing an epitaxial layer on the surface of the smoothed silicon wafer, the grown epitaxial layer being an extremely thin film having a thickness sufficient for causing LPDs on a surface of the grown epitaxial layer to be extinct.

3. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the pulling condition in the ingot manufacturing step comprises rapidly cooling the silicon ingot.

4. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the pulling condition in the ingot manufacturing step comprises rapidly cooling the silicon ingot.

5. The method of manufacturing an epitaxial silicon wafer as claimed in claim 3 , wherein the pulling condition in the ingot manufacturing step comprises further doping the silicon ingot with nitrogen.

6. The method of manufacturing an epitaxial silicon wafer as claimed in claim 4 , wherein the pulling condition in the ingot manufacturing step comprises further doping the silicon ingot with nitrogen.

7. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the annealing step and the epitaxial layer growing step are performed under isothermal and isobaric conditions.

8. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the annealing step and the epitaxial layer growing step are performed under isothermal and isobaric conditions.

9. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the annealing step comprises a step of smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is within a range of 1000° C. to 1200° C., whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped shallow and wide recesses.

10. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the annealing step comprises a step of smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is within a range of 1000° C. to 1200° C., whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped shallow and wide recesses.

11. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the annealing step comprises a step of smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is within a range of 1000° C. to 1200° C. and an annealing time is within a range of 10 seconds to 60 seconds, whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped, shallow and wide recesses.

12. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the annealing step comprises a step of smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is within a range of 1000° C. to 1200° C. and an annealing time is within a range of 10 seconds to 60 seconds, whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped, shallow and wide recesses.

13. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the annealing temperature in the annealing step is set to an epitaxial growth temperature.

14. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the annealing temperature in the annealing step is set to an epitaxial growth temperature.

15. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the annealing step and the epitaxial layer growing step are performed incessantly through a round of processes in a same epitaxial growth furnace.

16. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the annealing step and the epitaxial layer growing step are performed incessantly through a round of processes in an epitaxial growth furnace.

17. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the extremely thin film formed in the epitaxial layer growing step has a thickness within a range of 0.3 μm to 2 μm.

18. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the extremely thin film formed in the epitaxial layer growing step has a thickness within a range of 0.3 μm to 2 μm.

19. The method of manufacturing an epitaxial silicon wafer as claimed in claim 1 , wherein the extremely thin film formed in the epitaxial layer growing step has a thickness smaller than 0.4 μm.

20. The method of manufacturing an epitaxial silicon wafer as claimed in claim 2 , wherein the extremely thin film formed in the epitaxial layer growing step has a thickness smaller than 0.4 μm.

21. A method of manufacturing an epitaxial silicon wafer, comprising:

a silicon ingot manufacturing step of pulling a silicon ingot under a pulling condition in which an LSTD density assumes a volume of 1×10 6 defects/cm 3 or more so as to obtain shallow recessed pits on a surface of a silicon wafer, when the silicon ingot is manufactured by Czochralski technique;

a step of slicing a silicon wafer having the shallow recessed pits on the surface of the silicon wafer off the silicon ingot manufactured in the silicon ingot manufacturing step;

an annealing step of smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is within a range of 1000° C. to 1200° C., whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped, shallow and wide recesses; and

an epitaxial layer growing step of growing an epitaxial layer on the surface of the smoother silicon wafer, the grown epitaxial layer consisting of an extremely thin film having a thickness smaller than 0.4 μm sufficient for causing LPDs on a surface of the grown epitaxial layer to disappear, the epitaxial layer growing step being performed continuously with the annealing step in a single epitaxial growth furnace.

22. A method of manufacturing an epitaxial silicon wafer, comprising:

a silicon ingot manufacturing step of pulling a silicon ingot under a pulling condition in which a COP size becomes 130 nm or less or a perfect crystal so as to obtain shallow recessed pits on a surface of a silicon wafer, when the silicon ingot is manufactured by Czochralski technique;

a step of slicing a silicon wafer having the shallow recessed pits on the surface of the silicon off the silicon ingot manufactured in the silicon ingot manufacturing step;

an annealing step of smoothing the surface of the silicon wafer by annealing the sliced off silicon wafer under an annealing condition in which an annealing temperature is within a range of 1000° C. to 1200° C., whereby the shallow recessed pits on the surface of the silicon wafer are converted into gently-sloped, shallow and wide recesses; and

an epitaxial layer growing step of growing an epitaxial layer on the surface of the smoothed silicon wafer, the grown epitaxial layer consisting of an extremely thin film having a thickness smaller than 0.4 μm sufficient for causing LPDs on a surface of the grown epitaxial layer to be extinct, the epitaxial layer growing step being performed incessantly with the annealing step in an epitaxial growth furnace.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2006
From: TOGASHI, KAZUYA; DANBATA, MASAYOSHI; ARAI, KUNIAKI; MATSUMOTO, KAORI
To: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
Reel/Frame 018438/0585 →
Priority Claims (1)
JP 11-244097 · Aug 30, 1999 · national
Continuity (2)
Division 0965080200 · Aug 30, 2000
Related Publication 20030068502A1 · Apr 10, 2003