Patent Application
Utility
App. No. 10/300,791
· Confirmation No. 7314
Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method
Abandoned -- Failure to Respond to an Office Action
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-11-21 | TRNA |
Transmittal of New Application | 4 | View | |
| 2002-11-21 | A.PE |
Preliminary Amendment | 4 | View | |
| 2002-11-21 | SPEC |
Specification | 28 | View | |
| 2002-11-21 | CLM |
Claims | 4 | View | |
| 2002-11-21 | ABST |
Abstract | 1 | View | |
| 2002-11-21 | DRW |
Drawings-only black and white line drawings | 25 | View | |
| 2002-11-21 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Manabu Miura
Hyogo, JAPAN
Makoto Hatakenaka
Hyogo, JAPAN
Classification
USPC
365/194
G11C29/00
G11C29/028
G11C11/401
G11C29/50
G11C29/50012
Prosecution
- Examiner
- PHAM, LY D
- Art Unit
- 2818
- Docket No.
- 009683-415
- Confirmation No.
- 7314
Foreign Priority
2000-184445(P)
·
2000-06-20
·
JAPAN
Publication
- Pub. No.
- US20030067815A1
- Pub. Date
- 2003-04-10
No recorded assignments were found for this patent.
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Quick Facts
- App. No.
- 10/300,791
- Filed
- 2002-11-21
- Pub. No.
- US20030067815A1
- Examiner
- PHAM, LY D
- Art Unit
- 2818
External Links