Granted Patent
Utility
US 6,512,707
· Confirmation No. 8434
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE ALLOWING ACCURATE EVALUATION OF ACCESS TIME OF MEMORY CORE CONTAINED THEREIN AND ACCESS TIME EVALUATING METHOD
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-04-19 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-04-19 | SPEC |
Specification | 28 | View | |
| 2001-04-19 | CLM |
Claims | 4 | View | |
| 2001-04-19 | ABST |
Abstract | 1 | View | |
| 2001-04-19 | DRW |
Drawings-only black and white line drawings | 25 | View | |
| 2001-04-19 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Manabu Miura
Hyogo, JAPAN
Makoto Hatakenaka
Hyogo, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/194
G11C29/028
G11C11/401
G11C29/50
G11C29/50012
Prosecution
- Examiner
- PHAM, LY D
- Art Unit
- 2818
- Docket No.
- 009683-368
- Confirmation No.
- 8434
Foreign Priority
2000-184445(P)
·
2000-06-20
·
JAPAN
Publication
- Pub. No.
- US20010055226A1
- Pub. Date
- 2001-12-27
Patent Term Adjustment
0days
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2014-10-20
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-04-19
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Quick Facts
- Patent No.
- US 6,512,707
- App. No.
- 09/837,164
- Filed
- 2001-04-19
- Granted
- 2003-01-28
- Pub. No.
- US20010055226A1
- Examiner
- PHAM, LY D
- Art Unit
- 2818
- PTA
- 0 days
External Links