RAM having dynamically switchable access modes
View Patent ↗A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.
1. A method of switching a memory from a single cell per bit mode to a two cells per bit mode, comprising:
a) activating a wordline to access a memory cell in the single cell per bit mode;
b) latching a data bit from the memory cell with a bitline sense amplifier to provide a complementary data bit;
c) activating another wordline to access another memory cell such that both the wordline and the other wordline are simultaneously activated; and,
d) restoring the data bit into the memory cell and the complementary data bit into the other memory cell for operating the memory in the two cells per bit mode.
2. The method of claim 1 , wherein the memory includes DRAM cells, the DRAM cells being refreshed at a first refresh rate in the single cell per bit mode.
3. The method of claim 2 , wherein the DRAM cells are refreshed at a second refresh rate in the two cells per bit mode, where the second refresh rate is less than the first refresh rate to save power.
4. A method of switching a memory from a two cells per bit mode to a single cell per bit mode, comprising:
a) activating a pair of word lines simultaneously to access a pair of memory cells in the two cells per bit mode;
b) latching a data bit from one of the pair of memory cells and a complementary data bit from the other of the pair of memory cells with a bitline sense amplifier; and,
c) restoring the data bit into the memory cell for operating the memory in the single cell per bit mode.
5. The method of claim 4 , wherein the memory includes DRAM cells, the DRAM cells being refreshed at a first refresh rate in the single cell per bitmode.
6. The method of claim 5 , wherein the DRAM cells ore refreshed at a second refresh rate in the two cells per bit mode, where the second refresh rate is less than the first refresh rate to save power.
7. A method for switching a memory array between single cell per bit mode and two cells per bit mode of operation, comprising:
a) reading single cell per bit data from a memory cell in the single cell per bit mode of operation;
b) expanding the single cell per bit data to two bits of data complementary to each other;
c) writing one of the bits of data to the memory cell and the other bit of data to another memory cell;
d) reading the one bit of data from the memory cell and the other bit of data from the other memory cell simultaneously in the two cells per bit mode of operation; and,
e) writing the one bit of data to the memory cell as the single bit per cell data.
8. The method of claim 7 , wherein the step of reading single cell per bit data includes activating a wordline.
9. The method of claim 8 , wherein the step of expanding includes activating a second wordline.
10. The method of claim 7 , wherein the step of expanding includes latching the date with a bitline sense amplifier.
11. The method of claim 9 , wherein the step d) includes activating the wordline end the second wordline simultaneously.
12. The method of claim 11 , wherein the second wordline is de-activated before step e).
13. The method of claim 7 , wherein the memory array includes DRAM cells refreshed at a lower refresh rate during the two cells per bit mode than in the single cell per bit mode.