Patent Assignment
Reel/Frame 027698/0690
Assignment of Assignor's Interest
Recorded: 2012-02-13
Received: 2012-02-13
Pages: 12
Assignor
MOSYS, INC.
Executed: 2012-01-30
Assignee
INVENSAS CORPORATION
2702 ORCHARD PARKWAY, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(23)
Scalable Embedded Dram Array
Application:
12/048,176 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,280 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,264 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,286 →
Non-Volatile Memory in Cmos Logic Process
Application:
11/262,141 →
Transparent Error Correcting Memory That Supports Partial-Word Write
Application:
11/221,098 →
Word Line Driver for Dram Embedded in a Logic Process
Application:
11/166,856 →
Predictive Error Correction Code Generation Facilitating High-Speed Byte-Write in a Semiconductor Memory
Application:
10/997,604 →
High Speed Memory System
Application:
10/927,157 →
Method and Apparatus for Lengthening the Data-Retention Time of a Dram Device in Standby Mode
Application:
10/377,677 →
Dram Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
Application:
10/374,956 →
Ram Having Dynamically Switchable Access Modes
Application:
10/308,157 →
Method and Apparatus for Temperature Adaptive Refresh in 1T-Sram Compatible Memory Using the Subthreshold Characteristics of Mosfet Transistors
Application:
10/300,427 →
Method and Apparatus for Completely Hiding Refresh Operations in a Dram Device Using Clock Division
Application:
10/279,363 →
Method and Apparatus for Completely Hiding Refresh Operations in a Dram Device Using Multiple Clock Division
Application:
10/114,282 →
Ram Having Dynamically Switchable Access Modes
Application:
10/109,878 →
Reduced Topography Dram Cell Fabricated Using a Modified Logic Process and Method for Operating Same
Application:
10/043,386 →
Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same
Application:
10/007,334 →
Non-Volatile Memory System
Application:
09/948,163 →
Apparatus for Controlling Data Transfer Between a Bus and Memory Array and Method for Operating Same
Application:
09/851,713 →
Method and Apparatus for Completely Hiding Refresh Operations in a Dram Device Using Clock Division
Application:
09/846,093 →
Reduced Topography Dram Cell Fabricated Using a Modified Logic Process and Method for Operating Same
Application:
09/772,434 →
Single-Port multi-bank memory system having read and write buffers and method of operating same
Application:
09/768,908 →