System for and method of assessing chip acceptability and increasing yield
View Patent ↗The present invention includes a method for testing a chip, comprising the steps of measuring power drawn by the chip, calculating a test frequency using the measured power drawn by the chip, and determining performance of the chip at the calculated test frequency. The present invention also includes a system for testing a chip including a first sensor to measure power drawn by the chip, a controller to calculate a test frequency using the measured power drawn by the chip, and a second sensor to measure speed of the chip at the calculated test frequency.
1. A method for testing a chip, comprising:
measuring power drawn by the chip;
calculating a test frequency using the measured power drawn by the chip (Pm), thermal resistance for the chip model (Tja) and power drawn by a worst case chip for the chip model (Pwt); and
determining performance of the chip at the calculated test frequency.
2. The method of claim 1 further comprising:
testing the chip over a range of voltages and frequencies; and
characterizing the chip according to test results of the testing.
3. The method of claim 1 , wherein the calculating a test frequency further comprises:
determining a frequency at which the chip model specifies (Fs);
determining a slope of correlation between test data for chips of a model for the chip being tested and operating frequencies for the chip model (M);
determining an offset between test data for the chip model and specified operating frequency correlation (B);
determining a chip model function temperature (Ts);
determining junction temperature of the chip (Tt); and
determining a slope of maximum operating frequency as a function of temperature for the chip model (FTS).
4. The method of claim 3 , wherein the calculating a test frequency further comprises:
performing computation according to (Fs·M+B)+([Ts−(Tja·−(PWT−Pm))]−Tt)·FTS.
5. The method of claim 3 , wherein the chip model junction temperature (Ts) is a temperature for a worst case power situation with worst case incoming air temperature and worst case thermal reference.
6. The method of claim 1 further comprising:
bringing the chip to a predetermined temperature.
7. The method of claim 1 further comprising:
checking the chip for shorts and continuity of connections.
8. The method of claim 1 further comprising:
powering up the chip.
9. The method of claim 1 further comprising:
applying a reset signal to the chip.
10. The method of claim 1 further comprising:
testing the chip over a range of voltages and frequencies;
entering test results data in a database; and
characterizing the chip according to test results.
11. A method for testing a chip, comprising:
measuring power drawn by the chip;
calculating a test frequency calculating a test frequency comprising:
determining a frequency at which the chip must operate (Fs);
determining a slope of correlation between test data for chips of a model for the chip being tested and operating frequencies for the chip model (M);
determining an offset between test data for the chip model and specified operating frequency correlation (B);
determining a chip model junction temperature (Ts);
determining a junction temperature of the chip (Tt); and,
determining a slope of maximum operating frequency as a function of temperature for the chip model (FTS); and
determining performance of the chip at the calculated test frequency.
12. The method of claim 11 wherein the calculating a test frequency further comprises:
determining a thermal resistance for the chip model (Tja);
determining a power drawn by a worst case chip for the chip model (Pwt); and
determining a measured power drawn by the chip (Pm);
13. The method of claim 12 wherein the calculating a test frequency further comprises:
performing computations according to (Fs·M+B)+([Ts−(Tja·(PWT−PM))]−Tt)·FTS.
14. The method of claim 11 further comprising:
testing the chip over a range of voltages and frequencies; and
characterizing the chip according to test results of the testing.
15. The method of claim 11 wherein the chip model junction temperature (Ts) is a temperature for a worst case power situation with a worst case incoming air temperature and worst case thermal resistance.
16. The method of claim 11 further comprising:
bringing the chip to a predetermined temperature.
17. The method of claim 11 further comprising:
checking the chip for shorts and continuity of connections.
18. The method of claim 11 further comprising:
powering up the chip.
19. The method of claim 18 further comprising:
applying a reset signal to the chip.
20. The method of claim 11 further comprising:
testing the chip over a range of voltages and frequencies;
entering test result data in a database; and
characterizing the chip according to test results.
21. A method for testing a chip, comprising:
measuring power drawn by the chip;
calculating a test frequency said calculating comprising reducing a chip model junction temperature (Ts) by the product of a thermal resistance for the chip model (Tja) and the difference between a measured power drawn by the chip (Pm) and power drawn by a worst case chip for the chip model (Pwt); and
determining performance of the chip at the calculated test frequency.
22. The method of claim 21 wherein the calculating a test frequency comprises:
determines a frequency at which the chip must operate (Fs);
determining a slope of correlation between test data for chips of a model for the chip being tested and operating frequencies for the chip model (M);
determining an offset between test data for the chip model and specified operating frequency correlation (B);
determining a chip model junction temperature (Ts);
determining a junction temperature of the chip (Tt); and,
determining a slope a maximum operating frequency as a function of temperature for the chip model (FTS).