IP Library Granted Patent US 6,859,918
Granted Patent B2
US 6,859,918 · App. 10/313,325 · Granted Feb 22, 2005

Alleviating line end shortening by extending phase shifters

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Quick Facts
Patent No.
US 6,859,918
App. No.
10/313,325
Granted
Feb 22, 2005
Kind
B2
Abstract

One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.

Claims (38)

1. A method for compensating for line end shortening during an optical lithography process for manufacturing an integrated circuit, comprising:

receiving a specification for the integrated circuit;

identifying a line end within the specification that includes modifications to endcaps that were generated during an optical proximity correction process to compensate for line end shortening;

reducing the modifications generated during the optical proximity correction process; and

using a phase shifter to define at least a portion of the line end, thereby compensating for the line end shortening, wherein using the phase shifter involves extending the phase shifter past the line end.

2. The method of claim 1 , wherein extending the phase shifter involves extending the phase shifter so that it covers at least part of the line end, but does not extend past the line end.

3. The method of claim 1 , further comprising automatically checking design rules that specify a minimum distance between the phase shifter and other structures within the integrated circuit.

4. The method of claim 1 , wherein reducing the modifications generated during the optical proximity correction process involves completely removing the modifications.

5. The method of claim 1 , wherein reducing the modifications generated during the optical proximity correction process involves removing some, but not all of the modifications.

6. The method of claim 1 , wherein using the phase shifter to define at least a portion of the line end involves extending an existing phase shifter that defines a portion of an associated line so that the existing phase shifter defines at least a portion of the line end.

7. The method of claim 1 , wherein if the line end is not straight, the method further comprises replacing the line end with a straight line end.

8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for compensating for line end shortening during an optical lithography process for manufacturing an integrated circuit, the method comprising:

receiving a specification for the integrated circuit;

identifying a line end within the specification that includes modifications to endcaps that were generated during an optical proximity correction process to compensate for line end shortening;

reducing the modifications generated during the optical proximity correction process; and

using a phase shifter to define at least a portion of the line end, thereby compensating for the line end shortening, wherein using the phase shifter involves extending the phase shifter past the line end.

9. The computer-readable storage medium of claim 8 , wherein extending the phase shifter involves extending the phase shifter so that it covers at least part of the line end, but does not extend past the line end.

10. The computer-readable storage medium of claim 8 , wherein the method further comprises automatically checking design rules that specify a minimum distance between the phase shifter and other structures within the integrated circuit.

11. The computer-readable storage medium of claim 8 , wherein reducing the modifications generated during the optical proximity correction process involves completely removing the modifications.

12. The computer-readable storage medium of claim 8 , wherein reducing the modifications generated during the optical proximity correction process involves removing some, but not all of the modifications.

13. The computer-readable storage medium of claim 8 , wherein using the phase shifter to define at least a portion of the line end involves extending an existing phase shifter that defines a portion of an associated line so that the existing phase shifter defines at least a portion of the line end.

14. The computer-readable storage medium of claim 8 , wherein if the line end is not straight, the method further comprises replacing the line end with a straight line end.

15. A means for compensating for line end shortening during an optical lithography process for manufacturing an integrated circuit, comprising:

a receiving means for receiving a specification for the integrated circuit;

an identification means for identifying a line end within the specification that includes modifications to endcaps that were generated during an optical proximity correction process to compensate for line end shortening;

a reducing means for reducing the modifications generated during the optical proximity correction process; and

a phase shifting means for using a phase shifter to define at least a portion of the line end, thereby compensating for the line end shortening, wherein using the phase shifter involves extending the phase shifter past the line end.

16. The means of claim 15 , further comprising a design rule checking means for automatically checking design rules that specify a minimum distance between the phase shifter and other structures within the integrated circuit.

17. A semiconductor structure within an integrated circuit created through a process that compensates for line end shortening during an optical lithography process for manufacturing an integrated circuit, the process comprising:

receiving a specification for the integrated circuit;

identifying a line end within the specification that includes modifications to endcaps that were generated during an optical proximity correction process to compensate for line end shortening;

reducing the modifications generated during the optical proximity correction process; and

using a phase shifter to define at least a portion of the line end, thereby compensating for the line end shortening, wherein using the phase shifter involves extending the phase shifter past the line end.

18. A mask for use in fabricating an integrated circuit created through a process that compensates for line end shortening during an optical lithography process for manufacturing an integrated circuit, the process comprising:

receiving a specification for the integrated circuit;

identifying a line end within the specification that includes modifications to endcaps that were generated during an optical proximity correction process to compensate for line end shortening;

reducing the modifications generated during the optical proximity correction process; and

using a phase shifter to define at least a portion of the line end, thereby compensating for the line end shortening, wherein using the phase shifter involves extending the phase shifter past the line end.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2009
From: NUMERICAL TECHNOLOGIES, INC.
To: SYNOPSYS MERGER HOLDINGS, LLC
Reel/Frame 023719/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2005
From: SYNOPSYS MERGER HOLDINGS LLC
To: SYNOPSYS, INC.
Reel/Frame 015653/0738 →