Method and apparatus for on-wafer testing of an individual optical chip

1. A method for testing an optical chip formed on an uncut wafer, the wafer including at least a substrate and said optical chip including a chip waveguide having at least a core disposed above such substrate and a cladding layer disposed on said core, the optical chip being a planar optical waveguide having an axis, the method for testing comprising the steps of removing some portions of the waveguide to form an access site such that light exiting the planar optical waveguide is directed in a direction substantially different from the axis of the waveguide; and placing an optical probe along a propagation path of the exiting light, a trench formed by milling, said milling being performed by one of ion milling and FIB (Focused Ion Beam) technique.

2. A method for testing an optical chip formed on an uncut wafer, the wafer including at least a substrate and said optical chip including a chip waveguide having at least a core disposed above such substrate and a cladding layer disposed on said core, the optical chip being a planar optical waveguide having an axis, the method for testing comprising the steps of removing some portion of the waveguide to form an access site such that light exiting the planar optical waveguide is directed in a direction substantially different from the axis of the waveguide; and placing an optical probe along a propagation path of the exiting light, said optical probe including an input, said input being connected to one of a light source and a detector and the waveguide of said probe having a mode size and numerical aperture matched to the mode size and numerical aperture of the planar optical waveguide device of said optical chip.

3. The method of claim 2 , wherein said access site is a trench formed adjacent to said planar optical waveguide device, said trench having a depth extending to expose at least the waveguide core.

4. The method of claim 3 , wherein a sidewall of said trench forms an angle substantially at 45° to said axis.

5. The method of claim 3 , wherein said sidewall of said trench forms an angle within 8° from 45° to said optical waveguide.

6. The method of claim 3 , wherein said sidewall of said trench forms an angle at substantially 20° from 45° to said axis.

7. The method of claim 3 , further comprising the step of forming the trench by creating cuts with a dicing saw.

8. The method of claim 3 , further comprising the step of forming the trench by dry etching.

9. The method of claim 3 , further comprising the step of forming the trench by milling.

10. The method of claim 3 , further comprising the step of forming the trench by ablation.

11. The method of claim 3 , wherein one or more surfaces of said trench are made reflective.

12. The method of claim 11 , wherein one or more metals are applied to said surfaces to make reflective surfaces.

13. The method of claim 2 , wherein said probe is in the form of a waveguide.

14. The method of claim 2 , wherein the waveguide of said probe includes a core, the core being composed of a doped Silica including one of Ge doped Silica, BPSG, and Phosphorous doped Silica, and Silicon Oxynitride.

15. The method of claim 2 , wherein the waveguide of the probe includes a core, the core of said probe being composed of undoped Silica.

16. The method of claim 2 , wherein the waveguide of the probe includes a cladding layer, the cladding layer of said probe being composed of a doped Silica including one of fluorine doped Silica or boron doped Silica.

17. The method of claim 2 , wherein the waveguide of said core includes a cladding layer, the cladding layer of said probe being composed of undoped Silica.

18. The method of claim 2 , wherein said optical probe includes an input, said input being connected to one of a light source and a detector.

19. The method of claim 2 , wherein said waveguide of said probe is an optical fiber.

20. The method of claim 2 , wherein said optical chip is on a wafer that is still in process.

21. The method of claim 2 , further comprising the step of processing said waveguide to allow access to the optical chip.

22. The method of claim 2 , wherein an input and output of said planar optical device under test is located on the same side of the optical chip; and further comprising the step of testing the optical chip with a single probe.

23. The method of claim 2 , further comprising the step of placing an index matching fluid between said probe and said planar optical device.

24. The method of claim 2 , wherein said probe consists of multiple waveguides.

25. The method of claim 2 , wherein said probe is in the form of one of a fiber array, a waveguide array, a detector array, and a light emitter array.

26. The method of claim 2 , wherein said probe contains a combination of waveguides, light emitters and detectors.