Non-volatile semiconductor memory and process of fabricating the same
View Patent ↗A non-volatile semiconductor memory including at least one first gate electrode as a floating gate on a semiconductor substrate with intervention of a first insulating film as a tunnel oxide film; sidewall spacers on both sidewalls of the first gate electrode in a direction of a channel length; a bit line formed of an impurity diffusion region of a conductivity type different from the conductivity type of the semiconductor substrate in a surface layer of the semiconductor substrate by the side of the first gate electrode, wherein the bit line comprises a first bit line formed in self-alignment using the first gate electrode as a mask and a second bit line formed in self-alignment using the first gate electrode and the sidewall spacers as a mask.
1. A non-volatile semiconductor memory comprising:
at least one first gate electrode as a floating gate on a semiconductor substrate with intervention of a first insulating film as a tunnel oxide film;
sidewall spacers on both sidewalls of the first gate electrode in a direction of a channel length;
a bit line formed of an impurity diffusion region of a conductivity type different from the conductivity type of the semiconductor substrate in a surface layer of the semiconductor substrate by the side of the first gate electrode,
wherein the bit line comprises a first bit line formed in self-alignment using the first gate electrode as a mask and a second bit line formed in self-alignment using the first gate electrode and the sidewall spacers as a mask; and
wherein the second bit line has a higher impurity concentration than the first bit line.
2. A non-volatile semiconductor memory comprising:
at least one first gate electrode as a floating gate on a semiconductor substrate with intervention of a first insulating film as a tunnel oxide film;
sidewall spacers on both sidewalls of the first gate electrode in a direction of a channel length;
a bit line formed of an impurity diffusion region of a conductivity type different from the conductivity type of the semiconductor substrate in a surface layer of the semiconductor substrate by the side of the first gate electrode,
wherein the bit line comprises a first bit line formed in self-alignment using the first gate electrode as a mask and a second bit line formed in self-alignment using the first gate electrode and the sidewall spacers as a mask; and
wherein the semiconductor substrate is provided with a trench in a region adjacent to the sidewall spacer, and the second bit line is formed in a surface layer of the trench.
3. A non-volatile semiconductor memory according to claim 2 , wherein the trench is formed in self-alignment using the first gate electrode and the side wall spacers as a mask.
4. A non-volatile semiconductor memory comprising:
at least one first gate electrode as a floating gate on a semiconductor substrate with intervention of a first insulating film as a tunnel oxide film;
sidewall spacers on both sidewalls of the first gate electrode in a direction of a channel length;
a bit line formed of an impurity diffusion region of a conductivity type different from the conductivity type of the semiconductor substrate in a surface layer of the semiconductor substrate by the side of the first gate electrode,
wherein the bit line comprises a first bit line formed in self-alignment using the first gate electrode as a mask and a second bit line formed in self-alignment using the first gate electrode and the sidewall spacers as a mask; and
wherein the second bit line is deeper than the first bit line.