A power divider having metal capacitors is disclosed to detect and divide a frequency signal. The divide includes a first capacitor including first and second electrodes formed at a first portion of a substrate, a second capacitor including first and second electrodes formed at a second portion of the substrate, a first metal line connected to the second electrode of the first capacitor, a second metal line connected to the second electrode of the second capacitor, a poly resistor connected to a contact area of the first capacitor and to a contact area of the second capacitor, and a third metal line connected to the first and second metal lines to divide a signal flown through the first and second metal lines.
1. A power divider comprising:
a first capacitor including a first electrode, a dielectric layer, a capping layer and a second electrode, wherein the first electrode of the first capacitor is formed at a source/drain region of a first transistor in a first portion of a substrate;
a second capacitor including a first electrode, a dielectric layer, a capping layer and a second electrode, wherein the first electrode of the second capacitor is formed at a source/drain region of a second transistor formed at a second portion apart from the first portion of the substrate;
a first metal line connected to the second electrode of the first capacitor to transmit an AC power signal detected from the first capacitor;
a second metal line connected to the second electrode of the second capacitor to transmit an AC power signal detected from the second capacitor;
a poly resistor connected to a contact area of the first capacitor and the first metal line, and to a contact area of the second capacitor and the second metal line; and
a third metal line connected to the first and second metal lines to divide an AC power signal flown through the first and second metal lines in common, and to transmit the divided power signal.
2. The power divider as claimed in claim 1 , wherein the first and second capacitors is formed by the steps of:
defining the first electrodes at a predetermined portion of the first region of the first or second transistor,
sequentially depositing the dielectric layer and the capping layer on an entire surface of the substrate including the first or second transistor,
depositing a photoresist pattern on an upper part of the capping layer deposited on the substrate defining the first electrodes,
removing the capping layer and the dielectric layer according to the photoresist pattern,
depositing an insulating layer to cover the capping layer and the first or second transistor,
forming a contact area exposing the upper part of the capping layer by selectively removing the insulating layer, and
forming the second electrodes by burying said contact area with metal and by planarizing said contact area.
3. The power divider as claimed in claim 1 , wherein upper parts of source/drain regions and a gate electrode of the first or second transistor are salicided.
4. The power divider as claimed in claim 2 , wherein a process forming the second electrodes by burying and planarizing the contact area is performed in the same step with a process burying the contact area between source/drain of the first and second transistors on the substrate and an upper metal line.
5. The power divider as claimed in claim 4 , wherein the processes of forming the second electrodes and burying the contact area between the source/drain of the first and second transistors on the substrate and the upper metal line include the steps of:
depositing a glue layer,
depositing a metal plug, planarizing the metal plug, and
depositing a metal line.
6. The power divider as claimed in claim 4 , wherein the process of forming the second electrodes and burying the contact area between the source/drain of the first and second transistors on the substrate and the upper metal line include the steps of:
forming a trench and the contact area in dual daniascene type,
depositing a metal layer within the trench and the contact area, and
forming a metal line by planarizing the metal layer.
7. The power divider as claimed in claim 1 , wherein at least one of the dielectric layers of the first and second capacitors is formed of PECVD SiO 2 or PECVD SiN.
8. The power divider as claimed in claim 1 , wherein at least one of the capping layers of the first and second capacitors is formed of TiN.
9. The power divider as claimed in claim 1 , wherein each capacitance of the first and second capacitors is determined according to the size of an area of the corresponding capping layer.
10. The power divider as claimed in claim 1 , wherein the substrate is divided into active and field regions by a field oxide layer, and then a poly silicon layer is formed on the field oxide layer to form the poly resistor.
11. The power divider as claimed in claim 10 , wherein the poly resistor is salicided.
12. The power divider as claimed in claim 1 , wherein at least one of the first region of the first transistor and the first region of the second transistor is a drain region.