IP Library Granted Patent US 6,988,164
Granted Patent B1
US 6,988,164 · App. 10/320,588 · Granted Jan 17, 2006

Compare circuit and method for content addressable memory (CAM) device

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Quick Facts
Patent No.
US 6,988,164
App. No.
10/320,588
Granted
Jan 17, 2006
Kind
B1
Abstract

A content addressable memory (CAM) device ( 100 ) may include a number of sub-blocks ( 102 - 8 to 102 - 15 ) that can generate CAM search results. In a “search beyond” operation, sub-blocks ( 102 - 8 to 102 - 15 ) may be excluded from a search operation according to criteria, including a sub-block address and a soft-priority value. A CAM device may include a compare circuit ( 400 ) that may compare sub-block address values in a time division multiplexed fashion to establish priority from among multiple CAM sub-blocks.

Claims (52)

1. A content addressable memory (CAM) device, comprising:

an input select circuit that provides a first value associated with a first CAM portion during a first time period, and provides a second value associated with a second CAM portion during a second time period; and

at least one comparator circuit having at least two inputs, at least a first input of the comparator circuit being coupled to an output of the input select circuit.

2. The CAM device of claim 1 , wherein:

the input select circuit includes a multiplexer having a first input that receives the first value and a second input that receives the second value, and a control input coupled to a control signal.

3. The CAM device of claim 1 , wherein:

the first value is a first sub-block address common to the CAM entries of the first portion; and

the second value is a second sub-block address common to the CAM entries of the second portion.

4. The CAM device of claim 3 , wherein

the first and second sub-block addresses are multi-bit values that differ from one another by one bit.

5. The CAM device of claim 1 , further including:

an output select circuit that provides a first compare result from the at least one comparator circuit during the first time period, and provides a second compare result from the at least one comparator circuit during the second time period.

6. The CAM device of claim 5 , wherein

the output select circuit includes a de-multiplexer having first input coupled to the compare circuit and a control input coupled to a control signal.

7. The CAM device of claim 1 , wherein

at least a second input of the comparator circuit is coupled to receive a third value associated with a search command.

8. The CAM device of claim 1 , further including:

a first output store coupled to the at least one comparator circuit for storing a first compare result, and

a second output store coupled to the at least one comparator circuit for storing a second compare result.

9. A method of establishing priority from among portions of a content addressable memory (CAM) device, comprising the steps of:

comparing priority values associated with CAM entries of different portions of a CAM device at different time periods in a single comparator, where the different portions each include a plurality of CAM entries.

10. The method of claim 9 , wherein:

the priority values include sub-block address values for a CAM device including multiple sub-blocks of entries, each sub-block comprising a plurality of CAM entries.

11. The method of claim 10 , wherein:

comparing the priority values includes:

comparing a first sub-block address to a search sub-block address when a control signal has a first value, and

comparing a second sub-block address to the search sub-block address when the control signal has a second value.

12. The method of claim 9 , wherein:

the priority values include sub-block soft-priority values for a CAM device having multiple sub-blocks of entries, such sub-block soft-priority values being programmable.

13. The method of claim 9 , further including:

outputting compare results generated by comparing the priority values at different time periods.

14. The method of claim 13 , wherein:

the priority values include sub-block address values for a CAM device having multiple sub-blocks of entries; and

outputting compare results includes:

outputting a first compare result between a first sub-block address and a search sub-block address when a control signal has a first value, and

outputting a second compare result between a second sub-block address and the search sub-block address when the control signal has a second value.

15. The method of claim 9 , wherein:

the priority values include sub-block address values and sub-block soft-priority values for a CAM device having multiple sub-blocks of entries, the soft-priority values being programmable; and

comparing the priority values includes:

generating an ignore indication for a first sub-block if a search soft-priority value is greater than a first sub-block soft-priority value, or if the search soft-priority value is equal to the first sub-block soft-priority value and the search sub-block address value is greater than a first sub-block address, and

generating an ignore indication for a second sub-block if the search soft-priority value is greater than a second sub-block soft-priority value, or if the search soft-priority value is equal to the second sub-block soft-priority value and the search sub-block address value is greater than a second sub-block address value.

16. A magnitude comparator, comprising:

a circuit that compares a magnitude of a first search address element to a magnitude of a second search address element during a first predetermined time interval and compares a magnitude of a first search priority element to a magnitude of a second search priority element during a second predetermined time interval;

the first search priority element being a programmable value commonly associated with a plurality of first CAM entries, and

the second search priority element being a programmable value commonly associated with a plurality of second CAM entries.

17. The magnitude comparator of claim 16 , wherein:

the first search address element is an address commonly associated with a plurality of first CAM entries; and

the second search address element is an address commonly associated with a plurality of second CAM entries.

18. The magnitude comparator circuit of claim 16 , further including:

an input select circuit that selectively outputs the first search address element or first search priority element according to a control signal.

19. The magnitude comparator circuit of claim 18 , further including:

an output select circuit that selectively outputs a compare result between the first search address element and the second search address element or a compare result between the first search priority element and the second search priority element according to the control signal.

Assignments (8)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2011
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
Reel/Frame 026830/0141 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2007
From: CYPRESS SEMICONDUCTOR CORPORATION
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 018961/0327 →