Method and apparatus to limit current-change induced voltage changes in a microcircuit

1. An apparatus, comprising:

a pipeline control circuit to enable execution units in a pipeline coupled to the pipeline control circuit;

a digital throttle unit coupled to said pipeline control circuit to generate a compensating current signal based on which of the execution units are not enabled; and

a dummy load circuit coupled to said digital throttle unit to consume a current corresponding to said compensating current signal.

2. The apparatus of claim 1 , wherein said digital throttle unit includes first logic to contain current weights corresponding to currents consumed by said execution units when enabled.

3. The apparatus of claim 2 , wherein said digital throttle unit is to add said current weights corresponding to said execution units when disabled, and to compare to a first threshold value, giving a first result.

4. The apparatus of claim 3 , further comprising an accumulator to time average said first result creating a second result.

5. The apparatus of claim 4 , further comprising a comparator to compare said second result to a second threshold, to create an increment/decrement signal.

6. The apparatus of claim 5 , further comprising a counter to receive said increment/decrement signal.

7. The apparatus of claim 6 , wherein said counter to output said compensating current signal.

8. The apparatus of claim 6 , wherein said counter increments or decrements at a rate given by a selector.

9. The apparatus of claim 3 , further comprising a second logic to contain a compensating weight corresponding to said compensating current signal.

10. The apparatus of claim 9 , wherein said first result is modified by said compensating weight.

11. The apparatus of claim 1 , wherein said dummy load includes dummy load elements that may be turned on responsive to said compensating current signal.

12. An apparatus, comprising:

a first counter responsive to a clock switch enable signal and a clock switch type signal to produce a ramp current signal, wherein the clock switch enable signal to indicate a transition in a clock frequency and the clock switch type signal to indicate whether the transition in the clock frequency is high to low or low to high; and

a dummy load circuit coupled to said ramp current signal to consume a current corresponding to said ramp current signal.

13. The apparatus of claim 12 , wherein said first counter to set value to zero responsive to said clock switch enable signal when said clock switch type signal indicates a low frequency to high frequency switch.

14. The apparatus of claim 13 , wherein said first counter to delay said low frequency to high frequency switch.

15. The apparatus of claim 12 , wherein said first counter to set value to an initial value responsive to said clock switch enable signal when said clock switch type signal indicates a high frequency to low frequency switch.

16. The apparatus of claim 15 , wherein said initial value corresponds to a difference between a low frequency current consumption and a high frequency current consumption.

17. The apparatus of claim 12 , wherein said first counter to be clocked by a second counter.

18. An apparatus, comprising:

a pipeline control circuit to enable execution units in a pipeline;

a digital throttle unit coupled to said pipeline control circuit to generate a compensating current signal based on which execution units are enabled;

a first counter responsive to a clock switch enable signal and a clock switch type signal, to produce a ramp current signal, wherein the clock switch enable signal to indicate a transition in a clock frequency and the clock switch type signal to indicate whether the transition in the clock frequency is high to low or low to high; and

a dummy load circuit coupled to said digital throttle unit and first counter to consume said compensating current signal and to said ramp current signal.

19. The apparatus of claim 18 , further comprising an adder to add said compensating current signal and to said ramp current signal to form a composite current signal.

20. The apparatus of claim 19 , further comprising a decoder to map said composite current signal to dummy load circuit elements of said dummy load circuit.

21. A method, comprising:

determining which execution units are not in use in a pipeline;

determining a compensating current based on the execution units which are not in use; and

consuming said compensating current in a dummy load.

22. The method of claim 21 , wherein said determining a compensating current includes summing weights corresponding to current consumed by said execution units if operating, and then comparing an outcome of said summing to a first threshold.

23. The method of claim 22 , wherein said determining a compensating current includes time averaging a result of said comparing outcome, and then determining from said time averaging whether to increase or decrease said compensating current.

24. A method, comprising:

receiving a frequency shift enable;

determining whether a frequency shift will be low to high or high to low;

if high to low, setting a compensating current to an initial value and then decreasing said compensating current to zero over a first time period; and

if low to high, inhibiting said frequency shift, setting said compensating current to zero and then increasing said compensating current to said initial value over a second time period, and then permitting said frequency shift.

25. The method of claim 24 , wherein said decreasing said compensating current includes decreasing a value sent to a dummy load.

26. The method of claim 25 , wherein said decreasing a value includes clocking a counter at a selected clock rate.

27. The method of claim 24 , wherein said increasing said compensating current includes increasing a value sent to a dummy load.

28. The method of claim 27 , wherein said increasing a value includes clocking a counter at a selected clock rate.

29. A system, comprising:

a pipeline control circuit to enable execution units in a pipeline;

a digital throttle unit coupled to said pipeline control circuit to generate a compensating current signal based on which of the execution units of the pipeline are not enabled;

a dummy load circuit coupled to said digital throttle unit to consume a current corresponding to said compensating current signal; and

an alternating current power supply coupled to said dummy load circuit to supply said current.

30. The system of claim 29 , wherein said digital throttle unit includes first logic to contain current weights corresponding to currents consumed by said execution units when enabled.

31. The system of claim 30 , wherein said digital throttle unit is to add said current weights corresponding to said execution units when disabled, and to compare to a first threshold value, giving a first result.

32. The system of claim 31 , further comprising an accumulator to time average said first result creating a second result.

33. The system of claim 32 , further comprising a comparator to compare said second result to a second threshold, to create an increment/decrement signal.

34. A system, comprising:

a first counter responsive to a clock switch enable signal and a clock switch type signal to produce a ramp current signal, wherein the clock switch enable signal to indicate a transition in a clock frequency and the clock switch type signal to indicate whether the transition in the clock frequency is high to low or low to high;

a dummy load circuit coupled to said ramp current signal to consume a current corresponding to said ramp current signal; and

an alternating current power supply coupled to said dummy load circuit to supply said current.

35. The system of claim 34 , wherein said first counter to set value to zero responsive to said clock switch enable signal when said clock switch type signal indicates a low frequency to high frequency switch.

36. The system of claim 35 , wherein said first counter to delay said low frequency to high frequency switch.

37. The system of claim 34 , wherein said first counter to set value to an initial value responsive to said clock switch enable signal when said clock switch type signal indicates a high frequency to low frequency switch.