Timing control in data receivers and transmitters
View Patent ↗A Gigabit transceiver ( 1 ) has a receiver ( 2 ) and a transmitter ( 3 ). There is an ADC ( 5 ) in the receiver ( 2 ) for each channel (A, B, C, D). The ADCs ( 5 ) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs ( 2 ) operate off half of the oversampling rate. In the receiver ( 2 ) fractionally spaced equalisers (FSES, 6 ) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.
1. A communication circuit comprising a receiver and a transmitter, in which the receiver comprises an analog-to-digital converter for receiving a signal on each of a plurality of channels and the transmitter comprises a digital-to-analog converter for transmitting a signal on each of said channels,
characterised in that,
the receiver comprises means for driving each of the analog-to-digital converters with the same clock to oversample incoming symbol streams on the channels at a rate that is at least a factor of two greater than the symbol rate,
the transmitter comprises means for driving each of the digital-to-analog converters from the same clock as is used by the receiver, and
the communication circuit does not include circuitry to determine a phase of the signal received from said plurality of channels by the analog-to-digital converters.
2. The communication circuit as claimed in claim 1 , wherein the receiver comprises a digital filter for each of the plurality of channels for recovering an optimum phase.
3. The communication circuit as claimed in claim 1 , wherein the receiver comprises means for downsampling.
4. The communication circuit as claimed in claim 2 , wherein the receiver comprises a fractionally spaced equaliser associated with each of the plurality of channels, said each fractionally spaced equaliser comprising said digital filter and said down-sampling means.
5. The communication circuit as claimed in claim 4 , wherein the receiver comprises a fractionally spaced equaliser associated with each of the plurality of channels, said each fractionally spaced equaliser comprising said digital filter and said down-sampling means; and wherein said each fractionally spaced equaliser comprises a filter in which data values are separated by less than a symbol period in time, and means for combining the data values in a linear manner using coefficients to perform channel equalisation prior to the downsampling to the symbol rate.
6. The communication circuit as claimed in claim 1 , wherein the circuit comprises a single phase-locked loop circuit comprising means for locking to a frequency and driving all of the receiver analog-to-digital converters and the transmitter digital-to-analog converters.
7. The communication circuit as claimed in claim 1 , wherein the receiver comprises a timing recovery circuit comprising means for recovering a received master clock from incoming symbols.
8. The communication circuit as claimed in claim 1 , wherein the receiver comprises means for driving the analog-to-digital converters at close to or during a digital logic switching quiet period.
9. A transceiver comprising the communication circuit as claimed in claim 1 .
10. A communication circuit comprising:
a receiver comprising an analog-to-digital converter for receiving a signal in the form of an incoming symbol stream having a symbol rate on each of a plurality of channels, the receiver comprising circuitry for driving each of the analog-to-digital converters with the same clock to oversample respective incoming symbol streams on the channels at a rate that is at least a factor of two greater than the symbol rate; and
a transmitter comprising a digital-to-analog converter for transmitting a signal on each of said channels, the transmitter comprising circuitry for driving each of the digital-to-analog converters from the same clock as is used by te receiver;
wherein the communication circuit does not include circuitry to determine a phase of the signal received from said plurality of channels by the analog-to-digital converters.
11. The communication circuit as claimed in claim 10 , wherein the receiver comprises a digital filter for each of the plurality of channels for recovering an optimum phase.
12. The communication circuit as claimed in claim 10 , wherein the receiver comprises means for downsampling.
13. The communication circuit as claimed in claim 11 , wherein the receiver comprises a fractionally spaced equaliser associated with each of the plurality of channels, said each fractionally spaced equaliser comprising said digital filter and said down-sampling means.
14. The communication circuit as claimed in claim 13 , wherein the receiver comprises a fractionally spaced equaliser associated with each of the plurality of channels, said each fractionally spaced equaliser comprising said digital filter and said down-sampling means; and wherein said each fractionally spaced equaliser comprises a filter in which data values are separated by less than a symbol period in time, and means for combining the data values in a linear manner using coefficients to perform channel equalisation prior to the downsampling to the symbol rate.
15. The communication circuit as claimed in claim 10 , wherein the circuit comprises a single phase-locked loop circuit comprising means for locking to a frequency and driving all of the receiver analog-to-digital converters and the transmitter digital-to-analog converters.
16. The communication circuit as claimed in claim 10 , wherein the receiver comprises a timing recovery circuit comprising means for recovering a received master clock from incoming symbols.
17. The communication circuit as claimed in claim 10 , wherein the receiver comprises means for driving the analog-to-digital converters at close to or during a digital logic switching quiet period.
18. A transceiver comprising the communication circuit as claimed in claim 6 .