Methods and structures for metal interconnections in integrated circuits
View Patent ↗A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.
1. An integrated-circuit assembly comprising:
first and second integrated transistors;
a first layer including first and second conductive regions respectively contacting the first and second integrated transistors;
a silicon-germanium layer having oxidized and non-oxidized regions, with the non-oxidized region contacting the first conductive region.
2. The integrated-circuit assembly of claim 1 , wherein the first layer comprises at least one of a silicon oxide, a silicon nitride, or silicon oxynitride, and each conductive region comprises aluminum.
3. The integrated-circuit assembly of claim 2 , wherein the aluminum layer includes copper or silicon.
4. The integrated-circuit assembly of claim 1 , wherein the oxidized region includes a germanium oxide which is extractable to form a porous insulative region.
5. The integrated-circuit assembly of claim 1 , further comprising:
an aluminum layer contacting at least a portion of the non-oxidized region.
6. The integrated-circuit assembly of claim 1 , wherein the silicon-germanium layer has a thickness of approximately one micron.
7. An integrated-circuit assembly comprising:
first and second integrated transistors;
a first layer including first and second conductive regions respectively contacting the first and second integrated transistors;
a silicon-germanium layer having oxidized and non-oxidized regions, with the oxidized region having a portion substantially coplanar with a portion of the non-oxidized region, and with the non-oxidized region contacting the first conductive region.
8. The integrated-circuit assembly of claim 7 , wherein the first layer comprises at least one of a silicon oxide, a silicon nitride, or silicon oxynitride, and each conductive region comprises aluminum.
9. The integrated-circuit assembly of claim 7 , wherein the oxidized region includes a germanium oxide which is extractable to form a porous insulative region.
10. The integrated-circuit assembly of claim 7 , wherein the silicon-germanium layer has a thickness of approximately one micron.
11. The integrated-circuit assembly of claim 7 , further comprising: an aluminum layer contacting at least a portion of the non-oxidized region.
12. An integrated-circuit assembly comprising:
first and second integrated transistors;
a first layer including first and second conductive regions respectively contacting the first and second integrated transistors;
a silicon-germanium layer comprising between 10 and 40 percent germanium and having an oxidized and a non-oxidized region, with the oxidized region having a portion substantially coplanar with a portion of the non-oxidized region, and with the non-oxidized region contacting the first conductive region.
13. The integrated-circuit assembly of claim 12 , wherein the first layer comprises at least one of a silicon oxide, a silicon nitride, or silicon oxynitride, and each conductive region comprises aluminum.
14. The integrated-circuit assembly of claim 12 , wherein the oxidized region includes a geranium oxide which is extractable to form a porous insulative region.
15. The integrated-circuit assembly of claim 12 , wherein the silicon-germanium layer has a thickness of approximately one micron.
16. An integrated-circuit assembly comprising:
first and second integrated transistors;
a first layer including first and second conductive regions respectively contacting the first and second integrated transistors;
a silicon-germanium layer comprising between 10 and 40 percent germanium and having an oxidized and a non-oxidized region, with the oxidized region having a portion coplanar with a portion of the non-oxidized region, and with the non-oxidized region contacting the first conductive region,
an aluminum layer contacting at least a portion of the non-oxidized region; and
a zirconium layer contacting the aluminum layer.
17. The integrated-circuit assembly of claim 16 , wherein the first layer comprises at least one of a silicon oxide, a silicon nitride, or silicon oxynitride, and each conductive region comprises aluminum.
18. The integrated-circuit assembly of claim 16 , wherein the oxidized region includes a germanium oxide which is extractable to form a porous insulative region.
19. The integrated-circuit assembly of claim 16 , wherein the silicon-germanium layer has a thickness of approximately one micron and wherein the aluminum layer is between the silicon-germanium layer and the zirconium layer.
20. The integrated-circuit assembly of claim 16 , wherein the aluminum layer has a thickness of about 1.5 microns and the zirconium layer has a thickness in a range of 50-250 nanometers.