Transceiver having shadow memory facilitating on-transceiver collection and communication of local parameters
View Patent ↗The present invention relates to a register for a single chip multi-sublayer PHY. More specifically, the present invention relates to a transceiver module including a single chip multi-layer PHY having one or more shadow registers. The transceiver module includes one or more storage modules adapted to store transceiver module local data. The shadow registers are adapted to facilitate collection of the local data from the storage modules and communicate the collected data to another portion of the transceiver module and/or to the upper lever system using at least one interface communicating with the shadow register.
1. A single chip multi-sublayer PHY system comprising:
at least one register adapted to store local data; and
two interfaces, at least one of said two interfaces communicating with said register, wherein said two interfaces are adapted to enable communication with at least one EEPROM.
2. The system of claim 1 , further comprising at least one transmit module.
3. The system of claim 2 , wherein said at least one transmit module comprises PMD and XAUI transmit modules.
4. The system of claim 1 , further comprising at least one receive module.
5. The system of claim 4 , wherein said at least one receive module comprises PMD and XAUI receive modules.
6. The system of claim 1 , wherein said at least one interface comprises a management data input/output interface.
7. The system of claim 1 , wherein said at least one interface comprises an XAUI transmit and receive interface.
8. The system of claim 7 , wherein said XAUI transmit and receive interface comprises 4 channels of 3 Gigabit data received by and 4 channels of 3Gigabit data transmitted by the single chip multi-sublayer PHY.
9. The system of claim 1 , wherein said at least one interface comprises a PMD transmit and receive interface.
10. The system of claim 9 , wherein said PMD transmit and receive interface comprises a 10 Gigabit serial transmit differential interface and a 10 Gigabit serial receive differential interface.
11. The system of claim 1 , further comprising a 2-wire controller communicating with said at least one register and said two interfaces.
12. The system of claim 1 , further comprising a plurality of local registers.
13. A single chip multi-sublayer PHY system comprising:
at least one register adapted to store local data;
two interfaces, at least one of said two interfaces communicating with said register, said two interfaces adapted to enable communication with at least one EEPROM;
at least one transmit module; and
at least one receive module.
14. The system of claim 13 , wherein said at least one transmit module comprises PMD and XAUI transmit modules.
15. The system of claim 13 , wherein said at least one receive module comprises PMD and XAUI receive modules.
16. The system of claim 13 , wherein said at least one interface comprises a management data input/output interface.
17. The system of claim 13 , wherein said at least one interface comprises an XAUI transmit and receive interface.
18. The system of claim 17 , wherein said XAUI transmit and receive interface comprises 4 channels of 3 Gigabit data received by and 4 channels of 3 Gigabit data transmitted by the single chip multi-sublayer PHY.
19. The system of claim 13 , wherein said at least one interface comprises a PMD transmit and receive interface.
20. The system of claim 19 , wherein said PMD transmit and receive interface comprises a 10 Gigabit serial transmit differential interface and a 10 Gigabit serial receive differential interface.
21. The system of claim 13 , further comprising a 2-wire controller communicating with said at least one register and said two interfaces.
22. The system of claim 13 , further comprising a plurality of local registers.