IP Library Granted Patent US 7,037,733
Granted Patent B2
US 7,037,733 · App. 10/343,762 · Granted May 2, 2006

Method for measuring temperature, annealing method and method for fabricating semiconductor device

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Quick Facts
Patent No.
US 7,037,733
App. No.
10/343,762
Granted
May 2, 2006
Kind
B2
Abstract

When the emissivity ε on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ε, such as a first DPS film 15 used for forming a plug 15 A, a second DPS film 17 used for forming a capacitor lower electrode 17 A and a third DPS film 20 used for forming a capacitor upper electrode 20 A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ε, such as a DPS film, is formed on the reverse face of the substrate 10.

Claims (42)

1. A method for measuring a temperature comprising the steps of:

forming a doped polysilicon film on a top face and a reverse face of a substrate:

removing a portion of said doped polysilicon film having been formed on said reverse face of said substrate;

measuring emissivity ε on said reverse face of said substrate in a state where no doped polysilicon film is formed on said reverse face of said substrate while annealing said substrate; and

calculating a temperature of said substrate being annealed on the basis of said measured emissivity ε.

2. The method for measuring a temperature of claim 1 ,

wherein the step of measuring emissivity ε includes a step of measuring reflectance r on said reverse face of said substrate for measuring said emissivity ε by using said measured reflectance r.

3. An annealing method for performing annealing on a substrate by using an annealing system including a substrate placing section, a heating section for annealing said substrate placed on said substrate placing section and a measuring section for measuring emissivity ε of said substrate placed on said substrate placing section, comprising the steps of:

forming a doped polysilicon film on a top face and a reverse face of said substrate;

removing a portion of said doped polysilicon film having been formed on said reverse face of said substrate;

measuring said emissivity ε on said reverse face of said substrate in a state where no doped polysilicon film is formed on said reverse face of said substrate while annealing said substrate; and

performing the annealing on said substrate while controlling an annealing temperature for said substrate on the basis of said measured emissivity ε.

4. The annealing method of claim 3 ,

wherein the step of measuring emissivity ε includes a step of measuring reflectance r on said reverse face of said substrate for measuring said emissivity ε by using said measured reflectance r.

5. The annealing method of claim 3 , wherein said doped polysilicon film is simultaneously formed on said top face and said reverse face of said substrate.

6. The annealing method of claim 3 ,

wherein said heating section has a temperature gradient formed in a given region therein, and

the step of performing the annealing on said substrate includes a step of controlling said annealing temperature for said substrate by controlling a position for holding said substrate within said given region with said substrate placing section.

7. A method for fabricating a semiconductor device using an annealing system including a substrate placing section, a heating section for annealing a substrate placed on said substrate placing section and a measuring section for measuring emissivity ε of said substrate placed on said substrate placing section, comprising the steps of:

forming a doped polysilicon film on a top face and a reverse face of said substrate before placing said substrate on said substrate placing section;

removing a portion of said doped polysilicon film having been formed on said reverse face of said substrate before placing said substrate on said substrate placing section;

measuring said emissivity ε on a reverse face of said substrate with said measuring section while placing said substrate on said substrate placing section in a state where no doped polysilicon film is formed on said reverse face of said substrate while annealing said substrate with said heating section; and

performing the annealing on said substrate while controlling an annealing temperature for said substrate on the basis of said measured emissivity ε.

8. The method for fabricating a semiconductor device of claim 7 ,

wherein the step of measuring said emissivity ε includes a step of measuring reflectance r on said reverse face of said substrate for measuring said emissivity ε by using said measured reflectance r.

9. The method for fabricating a semiconductor device of claim 7 ,

wherein said doped polysilicon film is simultaneously formed on said top face and said reverse face of said substrate.

10. The method for fabricating a semiconductor device of claim 7 ,

wherein said heating section has a temperature gradient formed in a given region therein, and

the step of performing annealing on said substrate includes a step of controlling said annealing temperature for said substrate by controlling a position for holding said substrate within said given region with said substrate placing section.

11. A method for fabricating a semiconductor device using an annealing system including a substrate placing section, a heating section for annealing a substrate placed on said substrate placing section and a measuring section for measuring emissivity ε of said semiconductor substrate placed on said substrate placing section, comprising the steps of:

forming a doped polysilicon film in at least a memory cell region on a top face and a reverse face of said substrate before placing said substrate on said substrate placing section;

removing a portion of said doped polysilicon film having been formed on said reverse face of said substrate before placing said substrate on said substrate placing section;

measuring said emissivity ε on said reverse face of said substrate with said measuring section while placing said substrate on said substrate placing section in a state where no doped polysilicon film is formed on said reverse face of said substrate while annealing said substrate with said heating section; and

performing the annealing on said substrate while controlling an annealing temperature for said substrate on the basis of said measured emissivity ε.

12. The method for fabricating a semiconductor device of claim 11 ,

wherein the step of measuring said emissivity ε includes a step of measuring reflectance r on said reverse face of said substrate for measuring said emissivity ε by using said measured reflectance r.

13. The method for fabricating a semiconductor device of claim 11 ,

wherein said doped polysilicon film is simultaneously formed on said top face and said reverse face of said substrate.

14. The method for fabricating a semiconductor device of claim 11 ,

wherein said heating section has a temperature gradient formed in a given region therein, and

the step of performing annealing on said substrate includes a step of controlling said annealing temperature for said substrate by controlling a position for holding said substrate within said given region with said substrate placing section.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2020
From: RPX CORPORATION
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 051842/0494 →
RELEASE OF LIEN ON PATENTS Recorded Oct 21, 2019
From: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
To: RPX CORPORATION
Reel/Frame 050777/0983 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
RELEASE (REEL 038041 / FRAME 0001) Recorded Jan 2, 2018
From: JPMORGAN CHASE BANK, N.A.
To: RPX CORPORATION; RPX CLEARINGHOUSE LLC
Reel/Frame 044970/0030 →
SECURITY AGREEMENT Recorded Mar 9, 2016
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038041/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: PANASONIC CORPORATION (FORMERLY KNOWN AS MATSUSHITA ELECTRIC INDUSTRIAL, CO., LTD.)
To: RPX CORPORATION
Reel/Frame 032826/0585 →
CHANGE OF NAME Recorded Jan 10, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 031961/0079 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2003
From: SHIBATA, SATOSHI; HIRASE, JUNJI; SUGIYAMA, TATSUO; KANASAKI, EMI; KAWASE, FUMITOSHI; NAITO, YASUSHI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 014285/0142 →