IP Library Granted Patent US 6,715,133
Granted Patent Utility
US 6,715,133 · Confirmation No. 2227

METHOD FOR ADDING REDUNDANT VIAS ON VLSI CHIPS

⬇ PDF
Code Description Pages PDF
2022-04-14 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2022-01-26 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2022-01-26 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2022-01-24 PA.. Power of Attorney 3 View
2022-01-24 R3.73 Assignee showing of ownership per 37 CFR 3.73 3 View
2022-01-24 N417 Electronic Filing System Acknowledgment Receipt 2 View
2003-11-12 IFEE Issue Fee Payment (PTO-85B) 1 View
2003-01-16 TRNA Transmittal of New Application 2 View
2003-01-16 SPEC Specification 18 View
2003-01-16 CLM Claims 3 View
2003-01-16 ABST Abstract 1 View
2003-01-16 DRW Drawings-only black and white line drawings 10 View
2003-01-16 OATH Oath or Declaration filed 3 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
Patent No.
US 6,715,133
App. No.
10/345,559
Filed
2003-01-16
Granted
2004-03-30
Pub. No.
US20030106027A1
Art Unit
2812
PTA
0 days