Physical layer device having a SERDES pass through mode

1. A physical layer device (PLD), comprising:

a first serializer-deserializer (SERDES) device having a first parallel port;

a second SERDES device having a second parallel port;

a third SERDES device having a third parallel port; and

a path selector configurable to select between one of the following:

(i) a first signal path between the first and second parallel ports, and

(ii) a second signal path between the first and third parallel ports;

wherein the first signal path is configured to route the following between the first and second parallel ports:

(i) deserialized data signals between the first and second parallel ports, and

(ii) at least one data clock, recovered from and synchronized with at least one of the deserialized data signals.

2. The PLD of claim 1 , wherein each of the first, second and third parallel ports includes

(i) a deserializer output for transmitting parallel, deserialized data, and

(ii) a serializer input for receiving parallel data to be serialized.

3. The PLD of claim 1 , wherein

the first signal path is configured to route a first deserialized data signal from the first parallel port to the second parallel port, and a first data clock, synchronized with the first deserialized data signal, from the first parallel port to the second parallel port; and

the second SERDES device is configured to convert the first deserialized data signal into a first serial data signal according to the first data clock.

4. The PLD of claim 3 , wherein:

the first signal path is also configured to route a second deserialized data signal from the second parallel port to the first parallel port, and a second data clock, synchronized with the second deserialized data signal, from the second parallel port to the first parallel port; and

the first SERDES device is configured to convert the second deserialized data signal into a second serial data signal according to the second data clock.

5. The PLD of claim 1 , wherein the second signal path is configured to route

(i) deserialized data signals between the first and third parallel ports, and

(ii) at least one data clock, synchronized with at least one of the deserialized data signals, between the first and third parallel ports.

6. The PLD of claim 1 , further comprising:

a controller configured to produce a path selector control signal, wherein the path selector is selectively configurable to provide either the first signal path or the second signal path responsive to the path selector control signal.

7. The PLD of claim 1 , wherein the path selector includes multiplexer logic configurable to establish either the first path or the second path.

8. The PLD of claim 7 , wherein the second path of the path selector includes a digital section configured to process deserialized data signals from the first and third parallel ports.

9. The PLD of claim 1 , wherein:

the first SERDES device includes a first serial data input and a first serial data output coupled to a first serial interface of the PLD;

the second SERDES device includes a second serial data input and a second serial data output coupled to a second serial interface of the PLD; and

the third SERDES device includes a third serial data input and a third serial data output coupled to a third serial interface of the PLD.

10. The PLD of claim 9 , wherein the first serial interface is a media access control (MAC) interface.

11. The PLD of claim 9 , wherein the second serial interface is an optical fiber interface.

12. The PLD of claim 9 , wherein the third serial interface is a copper medium interface.

13. The PLD of claim 1 , wherein the first, second and third SERDES devices, and the path selector are all constructed on a common integrated circuit (IC) substrate.

14. A physical layer device (PLD) for interconnecting first, second and third devices capable of communicating over respective first, second and third serial interfaces, comprising:

a first Serializer-Deserializer (SERDES) device having a first serial port coupled to the first serial interface, and a first parallel port;

a second SERDES device having a second serial port coupled to the second serial interface, and a second parallel port;

a third SERDES device having a third serial port coupled to the third serial interface, and a third parallel port;

a controller for generating a path selector control signal; and

a path selector responsive to the path selector control signal, configurable to select between one of the following:

(i) a first signal path configured to route between the first and second parallel ports first bi-directional deserialized data signals, and a data clock, recovered and synchronized with at least one of the first bi-directional deserialized data signals; and

(ii) a second signal path configured to route between the first and third parallel ports second bi-directional deserialized data signals.

15. The PLD of claim 14 , wherein, when the path selector is configured to provide the first path, the first and second communication devices are able to exchange data with each other through the first and second serial interfaces, the first and second SERDES devices, and the path selector.

16. The PLD of claim 15 , wherein, when the path selector is configured to provide the second path, the first and third communication devices are able to exchange data with each other through the first and third serial interfaces, the first and second SERDES devices, and the path selector.

17. The PLD of claim 14 , wherein the first SERDES device is configured to deserialize serial data from the first serial interface, to produce at the first parallel port one of the first bi-directional deserialized data signals; and

the second SERDES device is configured to deserialize serial data from the second serial interface, to produce at the second parallel port another one of the first bi-directional deserialized data signals.