Multiple chip semiconductor packages
View Patent ↗A semiconductor package, containing two or more IC devices. The IC devices are oriented in the same manner and at least two IC devices are separated by a die paddle that is attached to the active face of one of the IC devices, inward of the electrical contact areas.
1. A semiconductor package, comprising:
a first IC device with a plurality of electrical connection areas on a periphery of an active face;
a die paddle, directly attached to the active face of the first IC device, inward of the electrical connection areas, the die paddle being sized such that it does not cover the plurality of electrical connection areas of the first IC device;
a second IC device, a passive face of the second IC device being directly attached to the die paddle, and having a plurality of electrical connection areas on an active face opposite the passive face; and
electrical connections between the plurality of electrical connection areas of the first and second IC devices and a plurality of external electrical terminals that protrude from the package, an end portion of at least one of the plurality of external electrical terminals being bent down such that the end portion is approximately level with the active face of the first IC device;
wherein the first and second IC devices, the die paddle, the electrical connections, and a portion of each of the plurality of external electrical terminals are enclosed by an encapsulation.
2. A semiconductor package according to claim 1 , wherein the plurality of electrical connection areas on the second IC device are arranged on a periphery of the active face; and further comprising:
a third IC device, a passive side of which is attached to the active side of the second IC device, inward of the electrical connection areas on the second IC device; and
electrical connections between a plurality of electrical connection areas on a third IC device and said plurality of external electrical terminals that protrude from the package.
3. A semiconductor package according to claim 1 , wherein the plurality of electrical connection areas on at least one of the first and second IC devices are wire bonded to the plurality of external electrical terminals.
4. A semiconductor package according to claim 1 , wherein the plurality of electrical connection areas on the first and second IC devices are wire bonded to the plurality of external electrical terminals.
5. A semiconductor package according to claim 1 , wherein the plurality of electrical connection areas on one of the first and second IC devices are connected to the plurality of external electrical terminals using tape automatic bonding.
6. A method of assembling a semiconductor packages comprising:
directly attaching a die paddle to an active face of a first IC device, inward of a plurality of electrical connection areas on a periphery of the active face of said first IC device;
forming electrical connections between said plurality of electrical connection areas on the first IC device and a plurality of external electrical terminals;
directly attaching a passive face of a second IC device to the die paddle;
forming electrical connections between the plurality of electrical contact areas on an active face of the second IC device and the plurality of external electrical terminals; and
enclosing the first and second IC devices, the die paddle, the electrical connections, and a portion of each of the plurality of external electrical terminals in an encapsulation,
bending down an end portion of at least one of the plurality of external electrical terminals such that the end portion is approximately level with the active face of the first IC device.
7. A method of assembling a semiconductor package according to claim 6 , wherein the plurality of electrical contact areas on the active face of the second IC device are arranged on a periphery of the active face; the method further comprising:
attaching a passive face of a third IC device to the active face of the second IC device, inward of the plurality of electrical contact areas on the second IC device; and
forming electrical connections between a plurality of electrical contact areas on the active face of the third IC device and the plurality of external electrical terminals.
8. A method of assembling a semiconductor package according to claim 6 , wherein the plurality of electrical connections between the plurality of external electrical terminals and the plurality of electrical contact areas of one of the first and second IC devices are formed by a wire bonding method.
9. A method of assembling a semiconductor package according to claim 6 , wherein the electrical connections between the plurality of external electrical terminals and the plurality of electrical contact areas of the first and second IC devices are formed by a wire bonding method.
10. A method of assembling a semiconductor package according to claim 6 , wherein the plurality of electrical connection between the plurality of external electrical terminals and the plurality of electrical contact areas of one of the first and second IC devices are formed by a tape automatic bonding method.
11. A semiconductor package according to claim 2 , wherein the plurality of electrical connection areas on at least one of the first, second, and third IC devices are wire bonded to the plurality of external electrical terminals.
12. A semiconductor package according to claim 2 , wherein the plurality of electrical connection areas on the first, second, and third IC devices are wire bonded to the plurality of external electrical terminals.
13. A semiconductor package according to claim 3 , wherein the plurality of electrical connection areas on the first and second IC devices are wire bonded to the plurality of external electrical terminals.
14. A semiconductor package according to claim 2 , wherein the plurality of electrical connection areas on one of the first, second, and third IC devices are connected to the plurality of external electrical terminals using tape automatic bonding.
15. A semiconductor package according to claim 3 , wherein the plurality of electrical connection areas on one of the first and second IC devices are connected to the plurality of external electrical terminals using tape automatic bonding.
16. A method of assembling a semiconductor package according to claim 7 , wherein the plurality of electrical connections between the plurality of external electrical terminals and the plurality of electrical contact areas of one of the first, second, and third IC devices are formed by a wire bonding method.
17. A method of assembling a semiconductor package according to claim 7 , wherein the plurality of electrical connections between the plurality of external electrical terminals and the plurality of electrical contact areas of the first, second, and third IC devices are formed by a wire bonding method.
18. A method of assembling a semiconductor package according to claim 8 , wherein the plurality of electrical connections between the plurality of external electrical terminals and the plurality of electrical contact areas of the first and second IC devices are formed by a wire bonding method.
19. A method of assembling a semiconductor package according to claim 7 , wherein the plurality of electrical connection between the plurality of external electrical terminals and the plurality of electrical contact areas of one of the first, second, and third IC devices are formed by a tape automatic bonding method.
20. A method of assembling a semiconductor package according to claim 8 , wherein the plurality of electrical connection between the plurality of external electrical terminals and the plurality of electrical contact areas of one of the first and second IC devices are formed by a tape automatic bonding method.
21. The semiconductor package according to claim 1 , wherein the passive face of the first IC device is free from attachment to a substrate.
22. The method of assembling a semiconductor package according to claim 6 , wherein the encapsulation is provided such that the passive face of the first IC device is free from attachment to a substrate.
23. A semiconductor package according to claim 1 , wherein the bent down end portion of each of the external electrical terminals includes a plurality of electrical connection areas which the electrical connection areas of the first and second IC devices can connect to.
24. A semiconductor package according to claim 23 wherein the plurality of electrical connection areas of the external electrical terminals are substantially level.
25. The semiconductor package of claim 1 , wherein electrical connections are made to the bent down end portion approximately level with the active face of the first IC device.
26. The method of claim 6 , wherein the electrical connections are formed on the bent down end portion.