Floating gate analog voltage feedback circuit

1. A floating gate circuit, comprising:

a) a first floating gate having a first charge stored thereon;

b) a second floating gate having a second charge stored thereon, wherein the difference in charge level between said first and second floating gates is a predetermined function of an arbitrary input set voltage that is capacitively coupled to said first floating gate during a set mode;

c) a first circuit coupled between said first and second floating gates for causing the voltage on said first floating gate to be compared to the voltage on said second floating gate during a read mode and for generating an output voltage; and

d) a feedback circuit for capacitively coupling said first circuit to said first floating gate during said read mode, for causing said floating gate circuit to reach a steady state condition such that said output voltage is approximately equal to said input set voltage.

2. The floating gate circuit of claim 1 , wherein said feedback circuit comprises a capacitor coupled between said first floating gate and said first circuit.

3. The floating gate circuit of claim 2 , wherein said capacitor is further used for capacitively coupling said input set voltage to said first floating gate during said set mode.

4. The floating gate circuit of claim 1 , wherein said floating gate circuit reaches a steady state condition during said read mode at the point where the voltage on said first floating gate is approximately equal to the voltage on said second floating gate, such that said output voltage is approximately equal to said input set voltage.

5. The floating gate circuit of claim 1 , said first circuit comprising:

a differential stage comprising a first, second, third and fourth transistor, each said transistor having a gate and a first and second terminal, wherein said first floating gate is the gate of said first transistor, said second floating gate is the gate of said second transistor, the first terminals of said first and second transistors are coupled together, the second terminals of said first and third transistors are coupled together and are further coupled to the gates of said third and fourth transistors, the second terminals of said second and fourth transistors are coupled together, and the first terminals of said third and fourth transistors are coupled together; and

a gain stage comprising a fifth transistor, having a gate and a first and second terminal, a current source, and a compensation capacitor, wherein the gate of said fifth transistor is coupled to the second terminals of said second and fourth transistors, the first terminal of said fifth transistor is coupled to the first terminals of said third and fourth transistors, the second terminal of said fifth transistor is coupled to said current source and to said feedback circuit, and said compensation capacitor is coupled between the gate and the second terminal of said fifth transistor.

6. A floating gate circuit, comprising:

a) a first floating gate having charge stored thereon;

b) a second floating gate having charge stored thereon, wherein the difference in charge level between said first and second floating gates is a predetermined function of an arbitrary input set voltage that is capacitively coupled to said first floating gate during a set mode;

c) a first circuit coupled between said first and second floating gates for causing the voltage on said first floating gate to be compared to the voltage on said second floating gate during a read mode and for generating an output voltage; and

d) a feedback circuit for capacitively coupling said first circuit to said first floating gate during said read mode, for causing said floating gate circuit to reach a steady state condition at the point where the voltage on said first floating gate is approximately equal to the voltage on said second floating gate, such that said output voltage is approximately equal to said input set voltage.

7. A floating gate circuit, comprising:

a) a first floating gate having charge stored thereon;

b) a second floating gate having charge stored thereon, wherein the difference in charge level between said first and second floating gates is a predetermined function of an input set voltage that is capacitively coupled to said first floating gate during a set mode;

c) a first circuit coupled between said first and second floating gates for causing the voltage on said first floating gate to be compared to the voltage on said second floating gate during a read mode and for generating an output voltage, said first circuit comprising:

a differential stage comprising a first, second, third and fourth transistor, each said transistor having a gate and a first and second terminal, wherein said first floating gate is the gate of said first transistor, said second floating gate is the gate of said second transistor, the first terminals of said first and second transistors are coupled together, the second terminals of said first and third transistors are coupled together and are further coupled to the gates of said third and fourth transistors, the second terminals of said second and fourth transistors are coupled together, and the first terminals of said third and fourth transistors are coupled together; and

a gain stage comprising a fifth transistor, having a gate and a first and second terminal, a current source, and a compensation capacitor, wherein the gate of said fifth transistor is coupled to the second terminals of said second and fourth transistors, the first terminal of said fifth transistor is coupled to the first terminals of said third and fourth transistors, the second terminal of said fifth transistor is coupled to said current source, and said compensation capacitor is coupled between the gate and the second terminal of said fifth transistor; and

d) a feedback circuit comprising a capacitor coupled between said first floating gate and the junction of the second terminal of said fifth transistor and said current source during said read mode, for causing said floating gate circuit to reach a steady state condition at the point where the voltage on said first floating gate is approximately equal to the voltage on said second floating gate, such that said output voltage is approximately equal to said input set voltage.

8. A floating gate circuit comprising:

a) a floating gate having a charge stored thereon during a set mode that is a function of an arbitrary input set voltage;

b) a first circuit coupled to said floating gate for comparing the voltage on said floating gate to a first voltage during a read mode and for generating an output voltage; and

c) a feedback circuit for capacitively coupling said first circuit to said floating gate during said read mode, for causing said floating gate circuit to reach a steady state condition such that said output voltage is approximately equal to but opposite in polarity to said input set voltage.

9. The floating gate circuit of claim 8 , wherein said feedback circuit comprises a capacitor coupled between said first floating gate and said first circuit.

10. The floating gate circuit of claim 8 , wherein said first voltage is ground, and said floating gate circuit reaches a steady state condition at the point where the voltage on said floating gate is approximately equal to zero volts, such that said output voltage is approximately equal to the negative of said input set voltage.

11. The floating gate circuit of claim 8 , wherein said first circuit comprises:

a differential stage comprising a first, second, third and fourth transistor, each said transistor having a gate and a first and second terminal, wherein said floating gate is the gate of said first transistor, the gate of said second transistor is coupled to said first voltage, the first terminals of said first and second transistors are coupled together, the second terminals of said first and third transistors are coupled together and are further coupled to the gates of said third and fourth transistors, the second terminals of said second and fourth transistors are coupled together, and the first terminals of said third and fourth transistors are coupled together; and

a gain stage comprising a fifth transistor, having a gate and a first and second terminal, a current source, and a compensation capacitor, wherein the gate of said fifth transistor is coupled to the second terminals of said second and fourth transistors, the first terminal of said fifth transistor is coupled to the first terminals of said third and fourth transistors, the second terminal of said fifth transistor is coupled to said current source and to said feedback circuit, and said compensation capacitor is coupled between the gate and the second terminal of said fifth transistor.

12. A floating gate circuit comprising:

a) a floating gate having a voltage programmed thereon during a set mode that is a function of an input set voltage;

b) a first circuit coupled to said floating gate for comparing the voltage on said floating gate to zero volts during a read mode and for generating an output voltage; and

c) a feedback circuit for capacitively coupling said first circuit to said floating gate during said read mode, for causing said floating gate circuit to reach a steady state condition at the point when the voltage on said floating gate is approximately equal to zero volts, such that said output voltage is approximately equal to the negative of said input set voltage.

13. A floating gate circuit comprising:

a) a floating gate having a charge stored thereon during a set mode that is a function of an input set voltage;

b) a first circuit coupled to said floating gate for comparing the voltage on said floating gate to zero volts during a read mode and for generating an output voltage, said first circuit comprising:

a differential stage comprising a first, second, third and fourth transistor, each said transistor having a gate and a first and second terminal, wherein said floating gate is the gate of said first transistor, the gate of said second transistor is coupled to said first voltage, the first terminals of said first and second transistors are coupled together, the second terminals of said first and third transistors are coupled together and are further coupled to the gates of said third and fourth transistors, the second terminals of said second and fourth transistors are coupled together, and the first terminals of said third and fourth transistors are coupled together; and

a gain stage comprising a fifth transistor, having a gate and a first and second terminal, a current source, and a compensation capacitor, wherein the gate of said fifth transistor is coupled to the second terminals of said second and fourth transistors, the first terminal of said fifth transistor is coupled to the first terminals of said third and fourth transistors, the second terminal of said fifth transistor is coupled to said current source, and said compensation capacitor is coupled between the gate and the second terminal of said fifth transistor; and

c) a feedback circuit comprising a capacitor coupled between said floating gate and the junction of the second terminal of said fifth transistor and said current source during said read mode, for causing said floating gate circuit to reach a steady state condition at the point when the voltage on said floating gate is approximately equal to zero volts, such that said output voltage is approximately equal to the negative of said input set voltage.