Microcontroller with multiple function blocks and clock signal control
View Patent ↗A microcontroller of the present invention includes: input/output ports; peripheral functional blocks, associated with the input/output ports, for performing predetermined functions; a clock signal generating circuit; a function selection decoder circuit for decoding a mode signal input from function selection pins and outputting a function selection signal; a clock signal controlling section for controlling supply/stop of a clock signal to each of the functional blocks in response to the function selection signal; and a port controlling block for setting functions of the input/output ports in response to the function selection signal.
1. A microcontroller comprising:
input/output ports;
functional blocks, each associated with one of the input/output ports, for performing predetermined functions;
a clock signal generating section, which generates a clock signal supplied to each of the functional blocks;
a clock signal controlling section, which controls supply/stop of the clock signal to the functional blocks in response to an externally-supplied mode signal;
a responding section, which outputs a response signal in place of the functional blocks, when the functional blocks are accessed while the clock signal is not supplied thereto, the signal indicating that the access is and a central processing unit, which outputs an address signal to the functional blocks, wherein the responding section outputs the response signal based on the address signal and the mode signal.
2. The microcontroller according to claim 1 , wherein the responding section outputs the response signal to the central processing unit to instruct the central processing unit to stop accessing the functional blocks.
3. The microcontroller according to claim 1 , wherein the responding section comprises a decoding circuit, which decodes the address signal;
and a logic circuit section, which outputs the response signal based on a signal output from the decoding circuit and the function selection signal.
4. The microcontroller according to claim 1 , further comprising a decoding section, which decodes the mode signal and outputs a result of decoding as a function selection signal, wherein the clock signal controlling section controls supply/stop of the clock signal to the functional blocks in response to the function selection signal.
5. The microcontroller according to claim 4 , further comprising a central processing unit, which outputs an address signal to the functional blocks, wherein the responding section outputs the response signal based on the address signal and the mode signal.
6. The microcontroller according to claim 5 , wherein the responding section outputs the response signal to the central processing unit to instruct the central processing unit to stop accessing the functional blocks.
7. The microcontroller according to claim 5 , wherein the responding section comprises
a decoding circuit for decoding the address signal, and
a logic circuit section for outputting the response signal based on the signal output from the decoding circuit and the function selection signal.