Method of manufacturing electronic device
View Patent ↗In a method of forming a circuit pattern including fine pattern features and fine space, a hard mask layer is patterned with a first pattern defined by eliminating the fine space for merging the pattern features. Thereafter the hard mask layer is shrank. Next, the hard mask layer is patterned with a second pattern that is defined on the basis of the fine space. Finally, the circuit pattern is formed in an underlying layer using the hard mask layer as a mask.
1. A method of manufacturing an electronic device for defining first and second circuit patterns separated by space, said method comprising the steps of:
(a) providing a hard mask layer on an underlying layer;
(b) forming a first cover pattern in said hard mask layer, said first cover pattern configured to cover a region defining said first and second circuit patterns, said first cover pattern further configured to cover a region for defining said space;
(c) after said step (b), omnidirectionally reducing in size said hard mask layer;
(d) after said step (c), forming a second cover pattern in said hard mask layer, said second cover pattern configured to cover said region for defining said first and second circuit patterns, while exposing said underlying layer in said region for defining said space; and
(e) after said step (d), defining said first and second circuit patterns in said underlying layer using said hard mask layer as a mask.
2. The method according to claim 1 , wherein said step (b) comprises the steps of:
(b-1) providing a photoresist on said hard mask layer;
(b-2) patterning said photoresist based on said first cover pattern;
(b-3) after said step (b-2), shrinking said photoresist; and
(b-4) patterning said hard mask layer using said photoresist after shrinkage as a mask.
3. The method according to claim 2 , wherein said step (b-3) is performed by ion implantation, electron beam cure, ultraviolet cure, or heat temperature bake.