High-speed serial bit stream multiplexing and demultiplexing integrated circuits

1. A bit stream multiplexer that couples a communication Application Specific Integrated Circuit (ASIC) to a high-speed bit stream media, the bit stream multiplexer comprising:

a first transmit data multiplexing integrated circuit having an input that receives a first plurality of transmit bit streams at a first bit rate from the communication ASIC and an output that produces an interface plurality of transmit bit streams at an interface bit rate;

a second transmit data multiplexing integrated circuit having an input that receives the interface plurality of transmit bit streams at the interface bit rate and an output that produces a single bit stream output at a line bit rate;

a loss of lock signal that the second transmit data multiplexing integrated circuit asserts to the first transmit data multiplexing integrated circuit when the second transmit data multiplexing integrated circuit loses lock of the interface plurality of transmit bit streams;

a media interface that receives the single bit stream output at the line bit rate and couples the single bit stream output at the line bit rate to the high-speed bit stream media;

wherein the interface plurality of transmit bit streams includes fewer transmit bit streams than the first plurality of transmit bit streams includes; and

wherein the interface plurality of transmit bit streams includes more than one bit stream.

2. The bit stream multiplexer of claim 1 , wherein:

the first plurality of transmit bit streams includes sixteen transmit bit streams; and

the interface plurality of transmit bit streams includes four transmit bit streams.

3. The bit stream multiplexer of claim 1 , wherein:

the first bit rate is nominally 2.5 Giga Bits per Second (GBPS); and

the interface bit rate is nominally 10 GBPS; and the line bit rate is nominally 40 GBPS.

4. The bit stream multiplexer of claim 1 , wherein the high-speed bit stream media comprises a fiber optic media.

5. The bit stream multiplexer of claim 1 , further comprising:

a Printed Circuit Board (PCB) upon which the first transmit data multiplexing integrated circuit, the second transmit data multiplexing integrated circuit, and the media interface are mounted; and

a communication ASIC connector coupled to the PCB and operably coupled to the first transmit data multiplexing integrated circuit.

6. The bit stream multiplexer of claim 1 , wherein:

the first transmit data multiplexing integrated circuit comprises a silicon Complementary Metal Oxide Semiconductor (CMOS) based integrated circuit; and

the second transmit data multiplexing integrated circuit comprises one of an Indium-Phosphate based integrated circuit or a Silicon-Germanium based integrated circuit.

7. The bit stream multiplexer of claim 1 , wherein:

in a first operation, the first transmit multiplexing integrated circuit provides a clock signal corresponding to the interface plurality of transmit bit streams; and

in a second operation, the second transmit multiplexing integrated circuit provides a clock signal corresponding to the interface plurality of transmit bit streams.

8. The bit stream multiplexer of claim 1 , wherein the single bit stream output at the line bit rate conforms to the OC-768 operating standard.

9. The bit stream multiplexer of claim 1 , wherein the single bit stream output at the line bit rate conforms to the SEL-768 operating standard.

10. The bit stream multiplexer of claim 1 , wherein the first plurality of transmit bit streams at the first bit rate conforms to the SFI-5 operating standard.

11. The bit stream multiplexer of claim 1 , wherein:

the first transmit data multiplexing integrated circuit is the master of the interface plurality of transmit bit streams when the loss of lock signal is not asserted; and

the second transmit data multiplexing integrated circuit is the master of the interface plurality of transmit bit streams when the loss of lock signal is asserted.

12. The bit stream multiplexer of claim 1 :

further comprising a first bit stream clock provided by the first transmit data multiplexing integrated circuit to the second transmit data multiplexing integrated circuit; and

wherein the first bit stream clock operates at a frequency corresponding to one-half of the interface bit rate.

13. The bit stream multiplexer of claim 12 , wherein:

the second bit stream clock has a nominal frequency of 5 GHz; and

the interface bit rate is 10 Giga Bits per Second (GBPS).

14. The bit stream multiplexer of claim 12 , wherein the second bit stream clock is physically centered with respect to the interface plurality of transmit bit streams.

15. A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC), the bit stream demultiplexer comprising:

a first receive data demultiplexing integrated circuit having an output that produces a first plurality of receive bit streams at a first bit rate to the communication ASIC and an input that receives an interface plurality of receive bit streams at an interface bit rate;

a second receive data demultiplexing integrated circuit having an output that produces the interface plurality of receive bit streams at the interface bit rate and an input that receives a single bit stream input at a line bit rate;

a loss of lock signal that the first receive data demultiplexing integrated circuit asserts to the second receive data demultiplexing integrated circuit when the first receive data demultiplexing integrated circuit loses lock of the interface plurality of receive bit streams;

a media interface that receives the single bit stream input from the high-speed bit stream media rate and couples the single bit stream input at the line bit rate to the second receive data demultiplexing integrated circuit;

wherein the interface plurality of receive bit streams includes fewer bit streams than the first plurality of receive bit streams includes; and

wherein the interface plurality of receive bit streams includes more than one bit stream.

16. The bit stream demultiplexer of claim 15 , wherein: the first plurality of receive bit streams includes sixteen receive bit streams; and the interface plurality of receive bit streams includes four receive bit streams.

17. The bit stream demultiplexer of claim 15 , wherein:

the first bit rate is nominally 2.5 Giga Bits per Second (GBPS); and

the interface bit rate is nominally 10 GBPS; and

the line bit rate is nominally 40 GBPS.

18. The bit stream demultiplexer of claim 15 , wherein the high-speed bit stream media comprises a fiber optic media.

19. The bit stream demultiplexer of claim 15 , further comprising:

a Printed Circuit Board (PCB) upon which the a first receive data demultiplexing integrated circuit, the second receive data demultiplexing integrated circuit, and the media interface are mounted; and

a communication ASIC connector coupled to the PCB and operably coupled to the first receive data demultiplexing integrated circuit.

20. The bit stream demultiplexer of claim 15 , wherein:

the first receive data demultiplexing integrated circuit comprises a silicon Complementary Metal Oxide Semiconductor (CMOS) based integrated circuit; and

the second receive data demultiplexing integrated circuit comprises one of an Indium-Phosphate based integrated circuit or a Silicon-Germanium based integrated circuit.

21. The bit stream demultiplexer of claim 15 , wherein:

in a first operation, the first receive multiplexing integrated circuit provides a clock signal corresponding to the interface plurality of receive bit streams; and

in a second operation, the second receive multiplexing integrated circuit provides a clock signal corresponding to the interface plurality of receive bit streams.

22. The bit stream demultiplexer of claim 15 , wherein the single bit stream output at the line bit rate conforms to the OC-768 operating standard.

23. The bit stream demultiplexer of claim 15 , wherein the single bit stream output at the line bit rate conforms to the SEL-768 operating standard.

24. The bit stream demultiplexer of claim 15 , wherein the first plurality of receive bit streams at the first bit rate conforms to the SFI-5 operating standard.

25. The bit stream demultiplexer of claim 15 , wherein:

the second receive data demultiplexing integrated circuit is the master of the interface plurality of receive bit streams when the loss of lock signal is not asserted; and

the first receive data demultiplexing integrated circuit is the master of the interface plurality of receive bit streams when the loss of lock signal is asserted.

26. The bit stream demultiplexer of claim 15 :

further comprising a second bit stream clock provided by the second receive data demultiplexing integrated circuit to the first receive data demultiplexing integrated circuit; and

wherein the second bit stream clock operates at a frequency corresponding to one-half of the interface bit rate.

27. The bit stream demultiplexer of claim 26 , wherein:

the second bit stream clock has a nominal frequency of 5 GHz; and

the interface bit rate is 10 Giga Bits per Second (GBPS).

28. The bit stream demultiplexer of claim 26 , wherein the second bit stream clock is physically centered with respect to the interface plurality of receive bit streams.

29. An interface that services a bit stream multiplexer that couples a communication Application Specific Integrated Circuit (ASIC) to a high-speed bit stream media, the interface comprising:

an interface plurality of transmit bit streams, each of which carries a bit stream operating at an interface bit rate;

an interface clock operating at a fraction of the interface bit rate;

wherein the interface interfaces a first transmit data multiplexing integrated circuit to a second transmit data multiplexing integrated circuit;

wherein the first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams at a first bit rate and produces the interface plurality of transmit bit streams at the interface bit rate;

wherein the second transmit data multiplexing integrated circuit receives the interface plurality of transmit bit streams at the interface bit rate and produces a single bit stream output at a line bit rate, the second transmit data multiplexing integrated circuit includes a loss of lock signal, which is asserted to the first transmit data multiplexing integrated circuit when the second transmit data multiplexing integrated circuit loses lock of the interface plurality of transmit bit streams;

wherein the interface plurality of transmit bit streams includes fewer transmit bit streams than the first plurality of transmit bit streams includes; and

wherein the interface plurality of transmit bit streams includes more than one bit stream.

30. The interface of claim 29 , wherein:

the first plurality of transmit bit streams includes sixteen transmit bit streams; and

the interface plurality of transmit bit streams includes four transmit bit streams.

31. The interface of claim 29 , wherein:

the first bit rate is nominally 2.5 Giga Bits per Second (GBPS); and

the interface bit rate is nominally 10 GBPS; and the line bit rate is nominally 40 GBPS.

32. The interface of claim 29 , wherein:

in a first operation, the first transmit multiplexing integrated circuit provides the interface clock; and

in a second operation, the second transmit multiplexing integrated circuit provides the interface clock.

33. The interface of claim 29 , wherein:

the first transmit data multiplexing integrated circuit is the master of the interface plurality of transmit bit streams when the loss of lock signal is not asserted; and

the second transmit data multiplexing integrated circuit is the master of the interface plurality of transmit bit streams when the loss of lock signal is asserted.

34. The interface of claim 29 , wherein:

the interface clock is provided by the first transmit data multiplexing integrated circuit to the second transmit data multiplexing integrated circuit; and

wherein the interface clock operates at a frequency corresponding to one-half of the interface bit rate.

35. The interface of claim 29 , wherein the interface clock is physically centered with respect to the interface plurality of transmit bit streams.

36. An interface that services a bit stream multiplexer that couples a communication Application Specific Integrated Circuit (ASIC) to a high-speed bit stream media, the interface comprising:

an interface plurality of receive bit streams, each of which carries a bit stream operating at an interface bit rate;

an interface clock operating at a fraction of the interface bit rate;

wherein the interface interfaces a first receive data demultiplexing integrated circuit to a second receive data demultiplexing integrated circuit;

wherein the first receive data demultiplexing integrated circuit receives a single bit stream input at a line bit rate and produces the interface plurality of receive bit streams at the interface bit rate;

wherein the second receive data demultiplexing integrated circuit receives the interface plurality of receive bit streams at the interface bit rate and produces a first plurality of receive bit streams at a first bit rate, the second receive data demultiplexing integrated circuit includes a loss of lock signal, which is asserted to the first receive data demultiplexing integrated circuit when the second receive data demultiplexing integrated circuit loses lock of the interface plurality of receive bit streams;

wherein the interface plurality of receive bit streams includes fewer receive bit streams than the first plurality of receive bit streams includes; and

wherein the interface plurality of receive bit streams includes more than one bit stream.

37. The interface of claim 36 , wherein:

the first plurality of receive bit streams includes sixteen receive bit streams; and

the interface plurality of receive bit streams includes four receive bit streams.

38. The interface of claim 36 , wherein:

the first bit rate is nominally 2.5 Giga Bits per Second (GBPS); and

the interface bit rate is nominally 10 GBPS; and the line bit rate is nominally 40 GBPS.

39. The interface of claim 36 , wherein:

in a first operation, the first receive demultiplexing integrated circuit provides the interface clock; and

in a second operation, the second receive demultiplexing integrated circuit provides the interface clock.

40. The interface of claim 36 , wherein:

the first receive data demultiplexing integrated circuit is the master of the interface plurality of receive bit streams when the loss of lock signal is not asserted; and

the second receive data demultiplexing integrated circuit is the master of the interface plurality of receive bit streams when the loss of lock signal is asserted.

41. The interface of claim 36 , wherein:

the interface clock is provided by the first receive data demultiplexing integrated circuit to the second receive data demultiplexing integrated circuit; and

wherein the interface clock operates at a frequency corresponding to one-half of the interface bit rate.

42. The interface of claim 36 , wherein the interface clock is physically centered with respect to the interface plurality of receive bit streams.