Digital signal processor architecture optimized for controlling switched mode power supply
View Patent ↗A switched mode power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output parameter of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a difference between the output parameter and a reference value, a digital filter providing a digital control output based on a sum of current and previous error signals and previous control outputs, the error signals comprising integers having a relatively low numerical range and said control outputs comprising integers having a relatively high numerical range, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output. The digital filter further comprises an asymmetric arithmetic unit adapted to combine the low range integers with the high range integers.
1. A power supply comprising:
at least one power switch adapted to convey power between respective input and output terminals of said power supply; and
a digital controller adapted to control operation of said at least one power switch responsive to an output parameter of said power supply, said digital controller comprising:
an analog-to-digital converter providing a digital error signal representing a difference between said output measurement and a reference value;
a digital filter providing a digital control output based on sum of present and previous error signals and previous control outputs, said error signals comprising integers having a relatively low numerical range and said control outputs comprising integers having a relatively high numerical range, said digital filter further comprising an asymmetric arithmetic unit adapted to combine said low range integers with said high range integers; and
a digital pulse width modulator providing a control signal to said at least one power switch, said control signal having a pulse width corresponding to said digital control output.
2. The power supply of claim 1 , wherein said analog-to-digital converter further comprises a windowed flash analog-to-digital converter.
3. The power supply of claim 1 , wherein said digital filter further comprises an infinite impulse response filter.
4. The power supply of claim 3 , wherein said infinite impulse response filter provides the following transfer function G(z):
G
(
z
)
=
PWM
(
z
)
VEd
(
z
)
=
C
0
+
C
1
·
z
-
1
+
C
2
·
z
-
2
+
…
+
C
n
·
z
-
n
1
-
B
1
·
z
-
1
-
B
2
·
z
-
2
-
…
-
B
n
·
z
-
n
wherein PWM(z) is the digital control output, VEd(z) is the error signal, C 0 . . . C n are input side coefficients, and B 1 . . . B n are output side coefficients.
5. The power supply of claim 3 , wherein said infinite impulse response filter further comprises a 3 rd order filter having the following transfer function G(z):
G
(
z
)
=
PWM
(
z
)
VEd
(
z
)
=
C
0
+
C
1
·
z
-
1
+
C
2
·
z
-
2
+
C
3
·
z
-
3
1
-
B
1
·
z
-
1
-
B
2
·
z
-
2
-
B
3
·
z
-
3
wherein PWM(z) is the digital control output, VEd(z) is the error signal, C 0 . . . C 3 are input side coefficients, and B 1 . . . B 3 are output side coefficients.
6. The power supply of claim 5 , wherein said infinite impulse response filter provides the following time discrete form transfer function:
PWM
k
′
=
1
K
1
·
(
C
0
′
·
VEd
k
+
C
1
′
·
VEd
k
-
1
+
C
2
′
·
VEd
k
-
2
+
C
3
′
·
VEd
k
-
3
+
B
1
′
·
PWM
k
-
1
′
+
B
2
′
·
PWM
k
-
2
′
+
B
3
′
·
PWM
k
-
3
′
)
wherein K 1 and K 2 are scaling factors selected such that the scaled PWM′ k signal will be in the range from 0 to K 2 −1 and wherein PWM′ k is the digital control output, VEd k is the error signal, C 0 . . . C 3 are input side coefficients, and B 1 . . . B 3 are output side coefficients, and:
PWM′ k =K 2 ·PWM′ k
C i ′=K 1 ′·K 2 ·C i
B i ′=K 1 ·B i .
7. The power supply of claim 1 , wherein said arithmetic unit further comprises a multiplier adapted to multiply two operands, wherein a first operand comprises a first bit size and a second operand comprises a second, substantially larger, bit size.
8. The power supply of claim 7 , wherein said first bit size is four.
9. The power supply of claim 7 , wherein said second bit size is twelve.
10. The power supply of claim 7 , wherein said arithmetic unit further comprises a first multiplexer coupled to said multiplier to provide said first operand, said first operand being selected from a group including said error signal, one of said previous error signals, and one of a plurality of first coefficients.
11. The power supply of claim 10 , wherein said arithmetic unit further comprises a second multiplexer coupled to said multiplier to provide said second operand, said second operand being selected from a group including said control output, one of said previous control outputs, and one of a plurality of second coefficients.
12. The power supply of claim 7 , wherein said arithmetic unit further comprises an adder adapted to add a product of said multiplier with second value selected from a group including zero and a previous sum of said adder.
13. The power supply of claim 12 , wherein said arithmetic unit further comprises a divider adapted to divide a sum of said adder by a scaling factor.
14. A method of controlling a switched mode power supply comprising at least one power switch adapted to convey power between input and output terminals of said power supply, said method comprising:
receiving an output measurement of said power supply;
sampling said output measurement to provide a digital error signal representing a difference between said output measurement and a reference value;
filtering said digital error signal to provide a digital control output based on a sum of previous error signals and previous control outputs; said error signals comprising integers having a relatively low numerical range and said control outputs comprising integers having a relatively high numerical range; and
providing a control signal to said at least one power switch, said control signal having a pulse width corresponding to said digital control output.
15. The method of claim 14 , wherein said filtering step further comprising asymmetrically combining said low range integers with said high range integers.
16. The method of claim 14 , wherein filtering step further comprises filtering said digital error signal using an infinite impulse response filter.
17. The method of claim 16 , wherein said filtering step further comprises filtering said digital error signal using an infinite impulse response filter having the following transfer function G(z):
G
(
z
)
=
PWM
(
z
)
VEd
(
z
)
=
C
0
+
C
1
·
z
-
1
+
C
2
·
z
-
2
+
…
+
C
n
·
z
-
n
1
-
B
1
·
z
-
1
-
B
2
·
z
-
2
-
…
-
B
n
·
z
-
n
wherein PWM(z) is the digital control output, VEd(z) is the error signal, C 0 . . . C n are input side coefficients, and B 1 . . . B n are output side coefficients.
18. The method of claim 16 , wherein said filtering step further comprising filtering said digital error signal using a 3 rd order infinite impulse response filter having the following transfer function G(z):
G
(
z
)
=
PWM
(
z
)
VEd
(
z
)
=
C
0
+
C
1
·
z
-
1
+
C
2
·
z
-
2
+
C
3
·
z
-
3
1
-
B
1
·
z
-
1
-
B
2
·
z
-
2
-
B
3
·
z
-
3
wherein PWM(z) is the digital control output, VEd(z) is the error signal, C 0 . . . C 3 are input side coefficients, and B 1 . . . B 3 are output side coefficients.
19. The method of claim 18 , wherein said infinite impulse response filter provides the following time discrete form transfer function:
PWM
k
′
=
1
K
1
·
(
C
0
′
·
VEd
k
+
C
1
′
·
VEd
k
-
1
+
C
2
′
·
VEd
k
-
2
+
C
3
′
·
VEd
k
-
3
+
B
1
′
·
PWM
′
k
-
1
+
B
2
′
·
PWM
′
k
-
2
+
B
3
′
·
PWM
′
k
-
3
)
wherein K 1 and K 2 are scaling factors selected such that the scaled PWM′ k signal will be in the range from 0 to K 2 −1 and wherein PWM′ k is the digital control output, VEd k is the error signal, C 0 . . . C 3 are input side coefficients, and B 1 . . . B 3 are output side coefficients, and:
PWM′ k =K 2 ·PWM′ k
C i′ =K 1 ·K 2 ·C i
B i ′=K 1 ·B i .
20. The method of claim 14 , wherein said filtering step further comprises multiplying two operands, wherein a first operand comprises a first bit size and a second operand comprises a second, substantially larger, bit size.
21. The method of claim 20 , wherein said first bit size is four.
22. The method of claim 20 , wherein said second it size is twelve.
23. The method of claim 20 , wherein said filtering step further comprises selecting said first operand from a group including said error signal, one of said previous error signals, and one of a plurality of first coefficients.
24. The method of claim 20 , wherein said filtering step further comprises selecting said second operand from a group including said control output, one of said previous control outputs, and one of a plurality of second coefficients.
25. The method of claim 20 , wherein said filtering step further comprises adding a product of said multiplying step with second value selected from a group including zero and a previous sum of said adder.
26. The method of claim 25 , wherein said filtering step further comprises dividing a sum of said adding step by a scaling factor.