IP Library Granted Patent US 7,215,366
Granted Patent B2
US 7,215,366 · App. 10/363,387 · Granted May 8, 2007

Tone correcting circuit and hue correcting circuit

Assignee: Sanyo Electric Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,215,366
App. No.
10/363,387
Granted
May 8, 2007
Kind
B2
Abstract

There are provided hue detecting means for detecting a hue component for each pixel from a first color difference signal R−Y and a second color difference signal B−Y, and gain controlling means for controlling for each pixel a gain for arbitrarily selected one of or an arbitrary combination of a luminance signal, a first color difference signal R−Y, and a second color difference signal B−Y depending on the detected hue component for each pixel.

Claims (21)

1. A tone correcting circuit comprising:

hue detecting means for detecting a hue component for each pixel from a first color difference signal R−Y and a second color difference signal B−Y; and

gain controlling means for controlling for each pixel a gain for arbitrarily selected one of or an arbitrary combination of a luminance signal, a first color difference signal R−Y, and a second color difference signal B−Y depending on the detected hue component for each pixel, thereby correcting a tone only for an arbitrary hue, wherein

the hue detecting means comprises a first bit shift circuit to which the first color difference signal (R−Y) is inputted, a second bit shift circuit to which a second color difference signal (B−Y) is inputted, and means for outputting for each pixel hue values corresponding to output values of both the bit shift circuits as hue components on the basis of a look-up table, and

each of the bit shift circuits cutting the number of bits composing an n-bit input signal to m which is smaller than n, cutting, when at least the respective uppermost bits in the color difference signals are both zero, the upper x bits in each of the color difference signals, letting x be the smaller one of the number of bits, out of the bits from the uppermost bit to the (m+1)-th bit in one of the color difference signals, which are continuously zero from the uppermost bit and the number of bits, out of the bits from the uppermost bit to the (m+1)-th bit in the other color difference signal, which are continuously zero from the uppermost bit, and further cutting the lower (n−m−x) bits in each of the color difference signals when x is smaller than (n−m).

2. The tone correcting circuit according to claim 1 , wherein a gain is set for each hue,

the gain controlling means comprising

gain calculating means for calculating for each pixel the gain corresponding to the hue component for each pixel detected by the hue detecting means on the basis of the set gain for each hue, and

means for providing for each pixel the gain for the pixel calculated by the gain calculating means as the gain for arbitrarily selected one of or the arbitrary combination of the luminance signal, the first color difference signal R−Y, and the second color difference signal B−Y.

3. A hue correcting circuit comprising:

hue detecting means for detecting a hue component for each pixel from a first color difference signal R−Y and a second color difference signal B−Y;

first offset providing means for providing an offset for each pixel to the first color difference signal R−Y depending on the detected hue component for each pixel; and

second offset providing means for providing an offset for each pixel to the second color difference signal B−Y, thereby correcting a hue only for an arbitrary hue, wherein

the hue detecting means comprises a first bit shift circuit to which the first color difference signal (R−Y) is inputted, a second bit shift circuit to which a second color difference signal (B−Y) is inputted, and means for outputting for each pixel hue values corresponding to output values of both the bit shift circuits as hue components on the basis of a look-up table, and

each of the bit shift circuits cutting the number of bits composing an n-bit input signal to m which is smaller than n, cutting, when at least the respective uppermost bits in the color difference signals are both zero, the upper x bits in each of the color difference signals, letting x be the smaller one of the number of bits, out of the bits from the uppermost bit to the (m+1)-th bit in one of the color difference signals, which are continuously zero from the uppermost bit and the number of bits, out of the bits from the uppermost bit to the (m+1)-th bit in the other color difference signal, which are continuously zero from the uppermost bit, and further cutting the lower (n−m−x) bits in each of the color difference signals when x is smaller than (n−m).

4. The hue correcting circuit according to claim 3 , wherein an offset is set for each hue,

each of the offset providing means comprising

saturation detecting means for detecting saturation for each pixel from the first color difference signal R−Y and the second color difference signal B−Y,

offset calculating means for calculating for each pixel an offset corresponding to the hue component for each pixel detected by the hue detecting means on the basis of the set offset for each hue,

offset producing means for multiplying the offset for each pixel calculated by the offset calculating means by the saturation of the corresponding pixel detected by the saturation detecting means, to produce for each pixel the offset corresponding to the saturation, and

means for providing for each pixel the offset for each pixel produced by the offset producing means to the color difference signal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2015
From: GODO KAISHA IP BRIDGE 1
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 035805/0310 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2014
From: SANYO ELECTRIC CO., LTD.
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032077/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2003
From: MORI, YUKIO; OKADA, SEIJI; MISE, TETSUO; YOSHIYAMA, MASAHIKO; MURATA, HARUHIKO; IINUMA, TOSHIYA; YAMASHITA, SYUGO
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 014167/0446 →
Priority Claims (3)
JP 2000-282363 · Sep 18, 2000 · national
JP 2000-292734 · Sep 26, 2000 · national
JP 2001-83406 · Mar 22, 2001 · national
Continuity (1)
Related Publication 20030193579A1 · Oct 16, 2003