Delay phase-locked loop device and clock signal generating method

1. A core logic chip that transmits out a parallel data according to a strobe signal and a parallel data signal, comprising:

a delay phase-locked loop (PLL) device for generating a plurality of output clock signals with different phases in response to a reference clock signal, comprising:

a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals;

a phase detector electrically connected to an output end of said controlled delay circuit, and generating an adjusting signal according to a phase relation between said reference clock signal and one of said output clock signals; and

a control circuit electrically connected to said phase detector and said controlled delay lines, and asserting a plurality of control signals to said controlled delay lines, respectively, in response to said adjusting signal in order to independently adjust the delay time of said output clock signals using said controlled delay lines, thereby obtaining four output signals P 0 , P 1 , P 2 and P 3 with different phases; and

a logic circuit for logically operating said four output signals P 0 , P 1 , P 2 and P 3 to generate a SEL-data signal and a SEL-strobe signal, based on which said parallel data signal and said strobe signal are generated, said logic circuit comprising:

a first inverter for inverting said output signal P 1 ;

a first AND gate for logically operating said output signal P 0 and said inverted output signal P 1 to obtain a first logic output R 1 ;

a second inverter for inverting said output signal P 3 ;

a second AND gate for logically operating said output signal P 2 and said inverted output signal P 3 to obtain a second logic output S 1 ; and

a first flip flop for outputting said SEL-data signal with said first logic output R 1 and said second logic output S 1 serving as reset and set terminals thereof, respectively.

2. The core logic chip according to claim 1 , wherein each of said controlled delay lines consists of a plurality of delay units in series.

3. The core logic chip according to claim 1 , wherein when said phase detector detects the phase of said one of said output clock signals is later than that of said reference clock signal, said adjusting signal is a delay-reduction adjusting signal; and when said phase detector detects the phase of said one of said output clock signals is earlier than that of said reference clock signal, said adjusting signal is a delay-extension adjusting signal.

4. The core logic chip according to claim 1 , wherein when said control circuit receives said adjusting signal, said control circuit enables a partial portion of said controlled delay lines for delay time adjustment.

5. The core logic chip according to claim 1 , wherein said delay circuit includes four delay lines for outputting four output clock signals according to four counted values, respectively, and said four counted values are independently adjusted by said control circuit.

6. The core logic chip according to claim 5 , further comprising a distribution table referred by said control circuit to determine said counted values.

7. The core logic chip according to claim 5 , wherein each of said plurality of controlled delay lines is precisely adjusted by a time period that depends on circuit design and layout of a hardware.

8. The core logic chip according to claim 1 , wherein said logic circuit further includes:

a third inverter for inverting said output signal P 2 ;

a third AND gate for logically operating said output signal P 1 and said inverted output signal P 2 to obtain a third logic output R 2 ;

a fourth inverter for inverting said output signal P 0 ;

a fourth AND gate for logically operating said output signal P 3 and said inverted output signal P 0 to obtain a fourth logic output S 2 ; and

a second flip flop for outputting said SEL-strobe signal with said third logic output R 2 and said fourth logic output S 2 serving as reset and set terminals thereof, respectively.

9. A core logic chip that transmits out a parallel data according to a strobe signal and a parallel data signal, comprising:

a delay phase-locked loop (PLL) device for generating a plurality of output clock signals with different phases in response to a reference clock signal, comprising:

a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals;

a phase detector electrically connected to an output end of said controlled delay circuit, and generating an adjusting signal according to a phase relation between said reference clock signal and one of said output clock signals; and

a control circuit electrically connected to said phase detector and said controlled delay lines, and asserting a plurality of control signals to said controlled delay lines, respectively, in response to said adjusting signal in order to independently adjust the delay time of said output clock signals using said controlled delay lines, thereby obtaining four output signals P 0 , P 1 , P 2 and P 3 with different phases; and

a logic circuit for logically operating said four output signals P 0 , P 1 , P 2 and P 3 to generate a SEL-data signal and a SEL-strobe signal, based on which said parallel data signal and said strobe signal are generated, said logic circuit comprising:

a first inverter for inverting said output signal P 2 ;

a first AND gate for logically operating said output signal P 1 and said inverted output signal P 2 to obtain a first logic output R 2 ;

a second inverter for inverting said output signal P 0 ; a second AND gate for logically operating said output signal P 3 and said inverted output signal P 0 to obtain a second logic output S 2 ; and

a first flip flop for outputting said SEL-strobe signal with said first logic output R 2 and said second logic output S 2 serving as reset and set terminals thereof, respectively.

10. The core logic chip according to claim 9 , wherein each of said controlled delay lines consists of a plurality of delay units in series.

11. The core logic chip according to claim 9 , wherein when said phase detector detects the phase of said one of said output clock signals is later than that of said reference clock signal, said adjusting signal is a delay-reduction adjusting signal; and when said phase detector detects the phase of said one of said output clock signals is earlier than that of said reference clock signal, said adjusting signal is a delay-extension adjusting signal.

12. The core logic chip according to claim 9 , wherein when said control circuit receives said adjusting signal, said control circuit enables a partial portion of said controlled delay lines for delay time adjustment.

13. The core logic chip according to claim 9 , wherein said delay circuit includes four delay lines for outputting four output clock signals according to four counted values, respectively, and said four counted values are independently adjusted by said control circuit.

14. The core logic chip according to claim 13 , further comprising a distribution table referred by said control circuit to determine said counted values.

15. The core logic chip according to claim 13 , wherein each of said plurality of controlled delay lines is precisely adjusted by a time period that depends on circuit design and layout of a hardware.