Multiple inverter system with low power bus ripples and method therefor
View Patent ↗A multiple inverter system is powered from a common energy source such as a battery. First and second inverters are coupled to the common energy source and drive corresponding motors. First and second controllers provide pulse width modulated signals, modulated with respect to first and second clock signals, respectively, to the respective first and second inverters. A capacitor coupled between a power bus and a ground bus smoothes power bus ripples caused by simultaneous switching. To reduce the size needed for the capacitor, different modulation schemes, such as center based interleaved, and leading and lagging edge coincident, are used when both motors are in the motoring mode or both motors are in the regeneration mode. However, the same modulation scheme is used when one motor is in the motoring mode and the other motor is in the regeneration mode.
1. A multiple inverter system for a vehicle comprising:
an energy source;
a capacitor coupled in parallel to said energy source;
a first inverter coupled to said energy source and adapted to drive a first motor,
a first controller having an output coupled to said first inverter for providing a first pulse width modulated signal thereto that is modulated in relation to a first clock signal;
a second inverter coupled to said energy source and adapted to drive a second motor, and
a second controller having an input for receiving a synchronization signal, and an output coupled to said second inverter for providing a second pulse width modulated signal thereto that is modulated in relation to a second clock signal, wherein said second controller uses said synchronization signal to generate said second clock signal having a predetermined relationship with respect to said first clock signal;
wherein said first and second clock signals are synchronized with respect to each other; and
wherein said first pulse width modulated signal is leading edge modulated with respect to said first clock signal and said second pulse width modulated signal is lagging edge modulated with respect to said second clock signal.
2. The multiple inverter system of claim 1 wherein said first and second clock signals are interleaved with respect to each other.
3. The multiple inverter system of claim 2 said first pulse width modulated signal is center based modulated with respect to said first clock signal and said second pulse width modulated signal is center based modulated with inspect to said second clock signal.
4. The multiple inverter system of claim 1 wherein said energy source comprises a battery.
5. The multiple inverter system of claim 1 wherein said capacitor is implemented as a bank of carbon capacitors.
6. The multiple inverter system of claim 1 wherein said first controller is characterized as being a master controller and said second controller is characterized as being a slave controller, and wherein said first controller further has an output for providing said synchronization signal to an input of said second controller.
7. The multiple inverter system of claim 1 further comprising a system controller coupled to said first and second controllers via a bus, for controlling a mode of operation of said first and second controllers.
8. A method for reducing the power bus ripples of a multiple inverter system comprising the steps of:
powering first and second inverters respectively coupled to first and second motors from a common power source;
generating a first pulse width modulated signal that is modulated in relation to a first clock signal;
driving said first inverter with said first pulse width modulated signal;
generating a second pulse width modulated signal that is modulated in relation to a second clock signal;
driving said second inverter with said second pulse width modulated signal; and
generating said first and second clock signals having a predetermined relationship with respect to each other;
wherein said step of generating said first and second clock signals comprises the step of synchronizing said first and second clock signals; and
wherein said step of generating said first pulse width modulated signal comprises the step of modulating said first pulse width modulated signal around a leading edge of said first clock signal, and wherein said step of generating said second pulse width modulated signal comprises the step of modulating said second pulse width modulated signal around a lagging edge of said second clock signal.
9. The method of claim 8 wherein said step of driving said first inverter comprises the step of driving said first inverter using a master controller, wherein said step of driving said second inverter comprises the step of driving said second inverter using a slave controller, and wherein the step of generating said first and second clock signals having said predetermined relationship with respect to each other comprises the step of providing a synchronization signal from said master controller to said slave controller.
10. The method of claim 8 wherein said step of providing said first and second clock signals comprises the step of interleaving said first and second clock signals.
11. The method of claim 10 wherein said step of generating said first pulse width modulated signal comprises the step of modulating said first pulse width modulated signal around a center of said first clock signal and wherein said step of generating said second pulse width modulated signal comprises the step of modulating said second pulse width modulated signal around a center of said second clock signal.
12. The method of claim 8 further comprising the step of smoothing power bus ripples of said common power source using a capacitor.
13. A method for reducing the power bus ripples of a multiple inverter system comprising the steps of:
powering first and second inverters respectively coupled to first and second motors from a common energy source;
driving said first inverter using a first pulse width modulation signal;
driving said second inverter using a second pulse width modulation signal;
generating said first and second pulse width modulation signals using the same modulation scheme when one of said first and second motors is in a motoring mode and the other one of said first and second motors is in a regeneration mode; and
generating said first and second pulse width modulation signals using different modulation schemes when either, both said first and second motors are in said motoring mode, or both said first and second motors are in said regeneration mode.
14. The method of claim 13 wherein said step of generating said first and second pulse width modulation signals using the same modulation scheme comprises the step of generating said first and second pulse width modulation signals using coincident center-based modulation.
15. The method of claim 13 wherein said step of generating said first and second pulse width modulation signals using different modulation schemes comprises the step of generating said first pulse width modulation signal using center based modulation with respect to a first clock signal and generating said second pulse width modulation signal using center based modulation with respect to a second clock signal that is interleaved with said first clock signal.
16. The method of claim 13 further comprising the step of placing said first and second motors into selected ones of said motoring mode and said regeneration mode using a common system controller.