5 Volt tolerant IO scheme using low-voltage devices
View Patent ↗Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.
1. A voltage tolerant circuit comprising:
a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions;
a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage; and
a switching transistor device adapted to switch between an intermediate power voltage and an IO power voltage.
2. The voltage tolerant circuit of claim 1 , wherein said voltage detect module comprises a voltage detect device adapted to determine whether said PAD voltage is high or low.
3. The voltage tolerant circuit of claim 1 , wherein said comparator comprises at least one device.
4. The voltage tolerant circuit of claim 1 , wherein said comparator comprises two PMOS transistor devices.
5. The voltage tolerant circuit of claim 1 , further comprising a tri-state module adapted to ensure that a PMOS transistor device will not turn on when said pad voltage exceeds said IO power supply voltage.
6. The voltage tolerant circuit of claim 5 , wherein said tri-state module comprises at least one device.
7. The voltage tolerant circuit of claim 5 , wherein said tri-state module comprises at least one PMOS transistor device.
8. The voltage tolerant circuit of claim 5 , wherein said tri-state module comprises at least one NMOS transistor device.
9. The voltage tolerant circuit of claim 1 , further comprising an overstress module.
10. The voltage tolerant circuit of claim 9 , wherein said overstress module comprises at least one device.
11. The voltage tolerant circuit of claim 9 , wherein said overstress module comprises three NMOS transistor devices.
12. The voltage tolerant circuit of claim 9 , wherein said overstress module is further adapted to prevent at least one transistor device from being overstressed.
13. The voltage tolerant circuit of claim 12 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said PAD Voltage.
14. The voltage tolerant circuit of claim 12 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said IO Power Supply Voltage.
15. A voltage tolerant circuit comprising:
a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions;
a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage;
a tri-state module adapted to ensure that a PMOS transistor device will not turn on when said pad voltage exceeds said IO power supply voltage; and
an overstress module adapted to prevent overstress of at least one device in a comparator module.
16. The voltage tolerant circuit of claim 15 , wherein said voltage detect module comprises a voltage detect device adapted to determine whether said PAD voltage is high or low.
17. The voltage tolerant circuit of claim 15 , wherein said comparator comprises at least one device.
18. The voltage tolerant circuit of claim 15 , wherein said comparator comprises two PMOS transistor devices.
19. The voltage tolerant circuit of claim 15 , wherein said tri-state module comprises at least one device.
20. The voltage tolerant circuit of claim 15 , wherein said tri-state module comprises at least one PMOS transistor device.
21. The voltage tolerant circuit of claim 15 , wherein said tri-state module comprises at least one NMOS transistor device.
22. The voltage tolerant circuit of claim 15 , wherein said overstress module comprises at least one device.
23. The voltage tolerant circuit of claim 15 , wherein said overstress module comprises three NMOS transistor devices.
24. The voltage tolerant circuit of claim 15 , wherein said overstress module is further adapted to prevent at least one transistor device from being overstressed.
25. The voltage tolerant circuit of claim 24 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said PAD Voltage.
26. The voltage tolerant circuit of claim 24 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said IO Power Supply Voltage.
27. The voltage tolerant circuit of claim 15 , further comprising a switching transistor device adapted to switch between an intermediate power voltage and an IO power voltage.
28. The voltage tolerant circuit of claim 15 , further comprising a transistor device adapted to decouple said PAD Voltage from at least one device in said comparator when said PAD voltage is less than a predetermined voltage.
29. The voltage tolerant circuit of claim 28 , wherein said predetermined voltage comprises a voltage of a core power supply plus a threshold voltage of said voltage detect circuit.
30. A voltage tolerant circuit comprising:
a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions;
a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage; and
a transistor device adapted to decouple said PAD voltage from at least one device in said comparator when said PAD voltage is less than a predetermined voltage.
31. The voltage tolerant circuit of claim 30 , wherein said voltage detect module comprises a voltage detect device adapted to determine whether said PAD voltage is high or low.
32. The voltage tolerant circuit of claim 30 , wherein said comparator comprises at least one device.
33. The voltage tolerant circuit of claim 30 , wherein said comparator comprises two PMOS transistor devices.
34. The voltage tolerant circuit of claim 30 , further comprising a tri-state module adapted to ensure that a PMOS transistor device will not turn on when said pad voltage exceeds said IO power supply voltage.
35. The voltage tolerant circuit of claim 34 , wherein said tri-state module comprises at least one device.
36. The voltage tolerant circuit of claim 34 , wherein said tri-state module comprises at least one PMOS transistor device.
37. The voltage tolerant circuit of claim 34 , wherein said tri-state module comprises at least one NMOS transistor device.
38. The voltage tolerant circuit of claim 30 , further comprising an overstress module.
39. The voltage tolerant circuit of claim 38 , wherein said overstress module comprises at least one device.
40. The voltage tolerant circuit of claim 38 , wherein said overstress module comprises three NMOS transistor devices.
41. The voltage tolerant circuit of claim 38 , wherein said overstress module is further adapted to prevent at least one transistor device from being overstressed.
42. The voltage tolerant circuit of claim 41 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said PAD Voltage.
43. The voltage tolerant circuit of claim 41 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said IO Power Supply Voltage.
44. The voltage tolerant circuit of claim 30 wherein said predetermined voltage comprises a voltage of a core power supply plus a threshold voltage of said voltage detect circuit.
45. A voltage tolerant circuit comprising:
a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions;
a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage; and
an overstress module comprising three NMOS transistor devices.
46. The voltage tolerant circuit of claim 45 , wherein said voltage detect module comprises a voltage detect device adapted to determine whether said PAD voltage is high or low.
47. The voltage tolerant circuit of claim 45 , wherein said comparator comprises at least one device.
48. The voltage tolerant circuit of claim 45 , wherein said comparator comprises two PMOS transistor devices.
49. The voltage tolerant circuit of claim 45 , further comprising a tri-state module adapted to ensure that a PMOS transistor device will not turn on when said pad voltage exceeds said IO power supply voltage.
50. The voltage tolerant circuit of claim 49 , wherein said tri-state module comprises at least one device.
51. The voltage tolerant circuit of claim 49 , wherein said tri-state module comprises at least one PMOS transistor device.
52. The voltage tolerant circuit of claim 49 , wherein said tri-state module comprises at least one NMOS transistor device.
53. The voltage tolerant circuit of claim 45 , wherein said overstress module comprises at least one device.
54. The voltage tolerant circuit of claim 45 , wherein said overstress module is further adapted to prevent at least one transistor device from being overstressed.
55. The voltage tolerant circuit of claim 54 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said PAD Voltage.
56. The voltage tolerant circuit of claim 45 , wherein said overstress module prevents said overstress when a voltage of a floating well is greater than said IO Power Supply Voltage.