Method of writing a group of data bytes in a memory and memory device
View Patent ↗The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.
1. A method of writing a group, having a certain number (N), of data bytes in a memory of a Low-Pin Count (LPC) memory device, the method comprising:
carrying out a first protocol cycle for unprotecting a memory sector of the memory in which to write the group of data bytes;
carrying out a second protocol cycle, after the first protocol cycle, for communicating a programming command to the memory device;
carrying out a third protocol cycle, after the second protocol cycle, for transmitting to the memory device a memory address and the whole group of data bytes to be written;
carrying out a writing phase of (8*N) data bits in the memory, the writing phase being carried out only once for the (N) data bytes and comprises writing a first byte of the group in a first address internally generated by resetting to zero the two least significant bits of the transmitted address, and writing the successive bytes respectively in memory addresses consecutive to the first internally generated address.
2. The method of claim 1 , wherein the number (N) of bytes of the group is not greater than four.
3. A memory device using a Low Pin Count (LPC) communication protocol, comprising:
a data bus;
an address bus;
a first internal bus;
a second internal bus;
a memory receiving data via the data bus to be written in the memory based upon a load data pulse, and receiving respective internal addresses through the address bus, and including a command interface receiving a write enable command and generating the load data pulse in synchronization therewith;
an input buffer receiving the data to be written in the memory and receiving memory addresses through an input bus and providing the data and memory addresses on the first internal bus;
a state machine coupled to the first internal bus, generating, upon receiving the load data pulse, internal addresses in which to write bytes of the data, a write enable command, and synchronization commands, and producing on the second internal bus bytes of data to be written in the memory;
a multiplexing circuit for transferring bytes of the data from the second internal bus to the data bus, when respective synchronization commands are received and when the write enable command is active; and
an address storage circuit for storing internal addresses generated by the state machine, and transferring the internal addresses on the address bus;
the state machine generating a first internal address to write a first byte by resetting to zero the two least significant bits of the memory address received through the first internal bus and comprising a sequential increment counter for sequentially updating the least significant bits of memory addresses, in response to the load data pulse, to generate successive internal addresses in which to write the successive bytes of data.
4. The device of claim 3 , wherein the state machine further comprises;
an interface coupled with the internal bus, producing on the second internal bus bytes of data to be written in the memory when it receives the write enable command;
an address generating circuit defining the counter, receiving memory addresses from the interface and generating internal addresses upon receiving the load data pulse;
a second data bus; and
a synchronization circuit including
an array of latches organized in banks of four latches each, each bank receiving from the interface bits of the data to be written and providing to the interface, through the second data bus the bits of data in groups of four bits when a respective synchronization command is received, and
a control circuit for the array of latches and generating the write enable command and the synchronization command for each group of bits.
5. The device of claim 4 , wherein the command interface generates the load data pulse for a byte of data to be written in a certain internal address, while the synchronization circuit transfers on the second data bus the byte of data to be written in the successive internal address.
6. The device of claim 5 , wherein the synchronization circuit comprises an array of 16 latches.
7. A memory device comprising;
a memory for storing data;
an input buffer receiving the data to be written in the memory and receiving memory addresses; and
a state machine connected to the input buffer for generating internal addresses from the memory addresses and supplying the data to be written in the memory, the state machine generating a first internal address for a first byte of data by resetting the least significant bits of the memory address received from the input buffer and generating successive internal addresses for successive bytes of data by incrementing the least significant bits of successive memory addresses received from the input buffer; the state machine comprising a synchronization circuit including an array of latches organized in banks of four latches each, each bank receiving bits of the data to be written and supplying bits of data in groups of four bits.
8. The device of claim 7 , wherein the synchronzation circuit comprises an array of sixteen latches.