IP Library › Assignment 031796/0348
Patent Assignment
Reel/Frame 031796/0348

Assignment of Assignor's Interest

Recorded: 2013-07-03 Pages: 255
Assignor
Assignee
MICRON TECHNOLOGY, INC.
8000 SO. FEDERAL WAY, BOISE, IDAHO, 83716-9632
Covered Properties (419)
Metallization Over Tungsten Plugs
Patent: 5,407,861 →
Application: 08/068,139 →
Method of Making nor-Type Rom with Ldd Cells
Patent: 5,407,852 →
Application: 08/084,971 →
Method and Apparatus for Filtering Digital Signals
Patent: 5,724,395 →
Application: 08/188,569 →
Method and Apparatus for Filtering High Resolution Digital Signals
Patent: 5,594,677 →
Application: 08/189,271 →
Nonvolatile Eprom, Eeprom of Flash-Eeprom Memory with Tunnel Oxide Protection
Patent: 5,497,345 →
Application: 08/196,572 →
Method of Reading, Erasing and Programming a Nonvolatile Flash-Eeprom Memory Array Using Source Line Switching Transistors
Patent: 5,587,946 →
Application: 08/212,907 →
Nonvolatile Flash-Eeprom Memory Array with Source Control Transistors
Patent: 5,508,956 →
Application: 08/214,049 →
Semiconductor Memory with Memory Matrix Comprising Redundancy Cell Columns Associated with Single Matrix Sectors
Patent: 5,469,389 →
Application: 08/219,204 →
Process for Realizing P-Channel Mos Transistors Having a Low Threshold Voltage in Semiconductor Integrated Circuits for Analog Applications
Patent: 5,534,448 →
Application: 08/282,408 →
Voltage Generator Circuit Providing Potentials of Opposite Polarity
Patent: 5,546,044 →
Application: 08/311,941 →
Method and Device for Supplying Negative Programming Voltages to Non-Volatile Memory Cells in a Non-Volatile Memory Device
Patent: 5,528,536 →
Application: 08/344,232 →
Method and Apparatus for Testing a Network with a Programmable Logic Matrix
Patent: 5,717,698 →
Application: 08/345,530 →
Monolithically Integrated Storage Device
Patent: 5,535,157 →
Application: 08/347,653 →
Stable Reference Voltage Generator Circuit
Patent: 6,392,469 →
Application: 08/347,788 →
Bias Circuit for a Memory Line Decoder Driver of Nonvolatile Memories
Patent: 5,499,217 →
Application: 08/348,461 →
Redundancy Circuitry for a Semiconductor Memory Device
Patent: 5,566,114 →
Application: 08/349,783 →
Integrated Circuitry for Checking the Utilization Rate of Redundancy Memory Elements in a Semiconductor Memory Device
Patent: 5,493,531 →
Application: 08/350,961 →
Integrated Programming Circuitry for an Electrically Programmable Semiconductor Memory Device with Redundancy
Patent: 5,548,554 →
Application: 08/365,154 →
End-Of-Count Detecting Device for Nonvolatile Memories
Patent: 5,594,703 →
Application: 08/365,510 →
Device for Detecting a Reduction in a Supply Voltage
Patent: 5,583,820 →
Application: 08/366,211 →
Circuit Device and Corresponding Method for Resetting Non-Volatile and Electrically Programmable Memory Devices
Patent: 5,586,077 →
Application: 08/366,212 →
Voltage Regulator for Programming Non-Volatile and Electrically Programmable Memory Cells
Patent: 5,519,656 →
Application: 08/366,259 →
Voltage Regulator for Non-Volatile Semiconductor Memory Devices
Patent: 5,576,990 →
Application: 08/367,538 →
Voltage Regulator for Non-Volatile Semiconductor Electrically Programmable Memory Devices
Patent: 5,659,516 →
Application: 08/368,211 →
Removable Bowling Ball Thumb Insert
Patent: 5,520,582 →
Application: 08/368,976 →
Circuit for Covering Initial Conditions When Starting-Up an Integrated Circuit Device
Patent: 5,612,641 →
Application: 08/380,309 →
Method for Programming and Testing a Nonvolatile Memory
Patent: 5,600,600 →
Application: 08/381,530 →
Method for Programming Redundancy Registers in a Column Redundancy Integrated Circuitry for a Semiconductor Memory Device, and Column Redundancy Integrated Circuitry
Patent: 5,602,786 →
Application: 08/389,599 →
Method and Circuit for Suppressing Data Loading Noise in Nonvolatile Memories
Patent: 5,541,884 →
Application: 08/391,147 →
Internal Timing Method and Circuit for Programmable Memories
Patent: 5,663,921 →
Application: 08/391,159 →
Method and Circuit for Timing the Loading of Nonvolatile-Memory Output Data
Patent: 5,515,332 →
Application: 08/391,160 →
Method for Programming Redundancy Registers in a Row Redundancy Integrated Circuitry for a Semiconductor Memory Device, and Row Redundancy Integrated Circuitry
Patent: 5,659,509 →
Application: 08/391,999 →
Regulation Circuit and Method for the Erasing Phase of Non-Volatile Memory Cells
Patent: 5,617,356 →
Application: 08/395,361 →
Reading Circuit Foran Integrated Semiconductor Memory Device
Patent: 5,627,790 →
Application: 08/408,589 →
Reference Signal Generating Method and Circuit for Differential Evaluation of the Content of Nonvolatile Memory Cells
Patent: 5,541,880 →
Application: 08/411,904 →
Flash-Eeprom Memory Array and Method for Biasing the Same
Patent: 5,638,327 →
Application: 08/412,162 →
Threshold Voltage Measuring Device for Memory Cells
Patent: 5,600,594 →
Application: 08/412,326 →
Redundancy Circuitry Layout for a Semiconductor Memory Device
Patent: 5,559,743 →
Application: 08/412,550 →
Memory Array Cell Reading Circuit with Extra Current Branch
Patent: 5,563,826 →
Application: 08/422,813 →
Sense Amplifier with Hysteresis
Patent: 5,715,204 →
Application: 08/432,838 →
Failure Tolerant Memory Device, in Particular of the Flash Eeprom Type
Patent: 5,682,349 →
Application: 08/454,650 →
Reading Circuit for Memory Cells
Patent: 5,710,739 →
Application: 08/476,547 →
Method for Testing an Electrically Erasable and Programmable Memory Device
Patent: 5,590,075 →
Application: 08/479,081 →
Nonvolatile Memory Cell and a Method for Forming the Same
Patent: 5,712,814 →
Application: 08/503,303 →
Circuit for Identifying a Memory Cell Having Erroneous Data Stored Therein
Patent: 5,687,124 →
Application: 08/521,304 →
Power-On Reset Circuit
Patent: 5,696,461 →
Application: 08/521,666 →
Byte Erasable Eeprom Fully Compatible with a Single Power Supply Flash-Eprom Process
Patent: 5,612,913 →
Application: 08/533,631 →
Memory Device Having Error Detection and Correction Function, and Methods for Reading, Writing and Erasing the Memory Device
Patent: 5,761,222 →
Application: 08/538,161 →
Integrated Circuit with Improved Immunity to Large Metallization Defects
Patent: 5,644,526 →
Application: 08/538,302 →
Decoder with Reduced Architecture
Patent: 5,742,187 →
Application: 08/560,090 →
Synchronization Device for Output Stages, Particularly for Electronic Memories
Patent: 5,633,834 →
Application: 08/560,324 →
Charge Pump Voltage Multiplier Circuit
Patent: 5,812,017 →
Application: 08/567,328 →
Process for the Production of a Semiconductor Device Having Better Interface Adhesion Between Dielectric Layers
Patent: 6,153,537 →
Application: 08/577,125 →
Programmable Multibit Register for Coincidence and Jump Operations and Coincidence Fuse Cell
Patent: 5,731,716 →
Application: 08/592,122 →
Serial Dichotomic Method for Sensing Multiple-Level Non-Volatile Memory Cells, and Sensing Circuit Implementing Such Method
Patent: 5,701,265 →
Application: 08/593,650 →
Integrated Circuitry for Checking the Utilization Rate of Redundancy Memory Elements in a Semiconductor Memory Device
Patent: 5,708,601 →
Application: 08/602,237 →
High-Voltage N-Channel Mos Transistor and Associated Manufacturing Process
Patent: 5,850,360 →
Application: 08/607,779 →
Programmable Memory with Single Bit Encoding
Patent: 5,850,361 →
Application: 08/628,587 →
Voltage Generator-Booster for Supplying a Pulsating Voltage Having Approximately Constant Voltage Levels
Patent: 5,914,867 →
Application: 08/631,574 →
Sense Amplifier Having Capacitively Coupled Input for Offset Compensation
Patent: 5,729,492 →
Application: 08/639,192 →
Eeprom Memory with Contactless Memory Cells
Patent: 5,717,636 →
Application: 08/642,325 →
Method of Manufacturing a Mos Integrated Circuit Having Components with Different Dielectrics
Patent: 6,114,203 →
Application: 08/644,892 →
Output Stage for Integrated Circuits, Particularly for Electronic Memories
Patent: 5,657,276 →
Application: 08/649,468 →
Nonvolatile Memory Device Having Sectors of Selectable Size and Number
Patent: 5,793,676 →
Application: 08/649,857 →
Negative Word Line Voltage Regulation Circuit for Electrically Erasable Semiconductor Memory Devices
Patent: 5,659,502 →
Application: 08/665,862 →
Process for Forming an Integrated Circuit Comprising Non-Volatile Memory Cells and Side Transistors and Corresponding Ic
Patent: 6,004,847 →
Application: 08/667,097 →
Process for Forming an Integrated Circuit Comprising Non-Volatile Memory Cells and Side Transistors of at Least Two Different Types, and Corresponding Ic
Patent: 5,856,221 →
Application: 08/670,179 →
Memory Device with Improved Yield and Reliability
Patent: 5,778,012 →
Application: 08/671,848 →
Method for Setting the Threshold Voltage of a Reference Memory Cell
Patent: 5,784,314 →
Application: 08/679,656 →
Charge Pump Circuit with Multiple Boost Stages
Patent: 5,760,497 →
Application: 08/684,192 →
Unbalanced Latch and Fuse Circuit Including the Same
Patent: 5,659,498 →
Application: 08/684,406 →
Modulated Slope Signal Generation Circuit, Particularly for Latch Data Sensing Arrangements
Patent: 5,737,268 →
Application: 08/684,431 →
Flash Eeprom with on-Chip Erase Source Voltage Generator
Patent: 6,195,291 →
Application: 08/687,145 →
Threshold Detecting Device
Patent: 5,847,584 →
Application: 08/688,956 →
Parallel-Dichotomic Serial Sensing Method for Sensing Multiple-Level Non-Volatile Memory Cells, and Sensing Circuit for Actuating Such Method
Patent: 5,729,490 →
Application: 08/690,059 →
Circuit for Reading Non-Volatile Memories
Patent: 5,734,610 →
Application: 08/690,530 →
Current Detecting Circuit
Patent: 5,764,570 →
Application: 08/691,796 →
Flash Eeprom with Integrated Device for Limiting the Erase Source Voltage
Patent: 6,507,067 →
Application: 08/692,936 →
Voltage Regulator for Semiconductor Non-Volatile Electrically Programmable Memory Device
Patent: 5,844,404 →
Application: 08/720,491 →
Parallel Programming Method of Memory Words and Corresponding Circuit
Patent: 5,781,474 →
Application: 08/722,378 →
Hierarchic Memory Device Having Auxiliary Lines Connected to Word Lines
Patent: 5,841,728 →
Application: 08/724,495 →
High Capacity Capacitor and Corresponding Manufacturing Process
Patent: 6,222,245 →
Application: 08/739,997 →
Analog Voltage-Signal Selector Device
Patent: 5,905,387 →
Application: 08/742,978 →
Negative Charge Pump Circuit for Electrically Erasable Semiconductor Memory Devices
Patent: 5,754,476 →
Application: 08/751,299 →
Erasing Method for a Non-Volatile Memory
Patent: 5,818,763 →
Application: 08/774,860 →
Device for Generating and Regulating a Gate Voltage in a Non-Volatile Memory
Patent: 5,822,247 →
Application: 08/775,111 →
Monolithically Integrated Programmable Device Having Elementary Modules Connected Electrically by Means of Memory Cells of the Flash Type
Patent: 6,005,411 →
Application: 08/777,296 →
Fabrication of Natural Transistors in a Nonvolatile Memory Process
Patent: 5,923,975 →
Application: 08/784,967 →
Boost Regulator
Patent: 5,821,806 →
Application: 08/787,494 →
Erase Voltage Control Circuit for an Electrically Erasable Non-Volatile Memory Cell
Patent: 5,721,707 →
Application: 08/787,907 →
Method for Erasing an Electrically Programmable and Erasable Non-Volatile Memory Cell
Patent: 5,784,319 →
Application: 08/788,530 →
Zero Consumption Power-On-Reset
Patent: 5,821,788 →
Application: 08/790,832 →
Multi-Level Memory Circuits and Corresponding Reading and Writing Methods
Patent: 5,859,795 →
Application: 08/791,348 →
High Voltages Detector Circuit and Integrated Circuit Using Same
Patent: 5,796,275 →
Application: 08/791,700 →
Decoding Hierarchical Architecture for High Integration Memories
Patent: 5,854,770 →
Application: 08/791,746 →
Process of Fabricating Tunnel-Oxide Nonvolatile Memory Devices
Patent: 5,817,557 →
Application: 08/792,893 →
Method for Improving the Intermediate Dielectric Profile, Particularly for Non-Volatile Memories
Patent: 5,894,065 →
Application: 08/802,619 →
Process for Fabricating a Microtip Cathode Assembly for a Field Emission Display Panel
Patent: 6,000,980 →
Application: 08/807,113 →
Electrically Programmable Non-Volatile Memory Cells Device for a Reduced Number of Programming Cycles
Patent: 5,926,416 →
Application: 08/807,574 →
Circuit for the Generation and Reset of Timing Signal Used for Reading a Memory Device
Patent: 5,793,699 →
Application: 08/811,386 →
Circuit for Immunizing an Integrated Circuit from Noise Affecting Enable Signals of the Integrated Circuit
Patent: 5,903,166 →
Application: 08/811,548 →
Integrated Device with Pads
Patent: 5,923,076 →
Application: 08/811,577 →
Address Transition Detection Circuit
Patent: 5,815,464 →
Application: 08/811,869 →
Non-Volatile Memory Device Having Optimized Management of Data Transmission Lines
Patent: 5,831,891 →
Application: 08/812,595 →
Timesharing Internal Bus, Particularly for Non-Volatile Memories
Patent: 6,438,669 →
Application: 08/813,687 →
Publication: US 2001/0042157
Method for Recovering Failed Memory Devices
Patent: 6,055,665 →
Application: 08/816,766 →
Circuit for Detecting the Coincidence Between a Binary Information Unit Stored Therein and an External Datum
Patent: 5,959,917 →
Application: 08/819,519 →
Sectorized Electrically Erasable and Programmable Non-Volatile Memory Device with Redundancy
Patent: 5,854,764 →
Application: 08/821,804 →
Row Decoding Circuit for Semiconductor Non-Volatile Electrically Programmable Memory and Corresponding Method
Patent: 5,848,013 →
Application: 08/824,616 →
High-Voltage-Resistant Mos Transistor, and Corresponding Manufacturing Process
Patent: 5,977,591 →
Application: 08/824,888 →
Voltage Booster for Memory Devices
Patent: 5,805,435 →
Application: 08/824,958 →
Data Sensing Timing Modulating Circuit, Particularly for Non-Volatile Memories
Patent: 5,881,001 →
Application: 08/825,098 →
Circuit and Method to Adjust Memory Timing
Patent: 5,886,945 →
Application: 08/825,138 →
Standby Voltage Boosting Stage and Method for a Memory Device
Patent: 5,889,723 →
Application: 08/826,008 →
Pulse Generation Circuit and Method for Synchronized Data Loading in an Output Pre-Buffer
Patent: 5,859,810 →
Application: 08/826,009 →
Driver Device for Selection Lines for a Multiplexer, to Be Used in a Wide Range of Supply Voltages, Particularly for Non-Volatile Memories
Patent: 5,751,654 →
Application: 08/826,223 →
Nonvolatile Memory Device Capable of Reading Data with an Appropriate Self-Timing and a Reduced Number of Reference Lines
Patent: 5,946,237 →
Application: 08/826,489 →
System for Determining the Programmed/Non Programmed Status of a Memory Cell
Patent: 5,864,513 →
Application: 08/827,409 →
Method and Apparatus for Redundancy Management of Non-Volatile Memories
Patent: 5,838,619 →
Application: 08/828,039 →
Gain Modulated Sense Amplifier
Patent: 5,901,087 →
Application: 08/828,790 →
Circuit and Method for Generating a Power-on Reset Signal
Patent: 5,959,476 →
Application: 08/828,791 →
Voltage Regulator for Programming Electrically Programmable Non-Volatile Memory Cells in a Cell Matrix
Patent: 6,175,521 →
Application: 08/833,336 →
Flash-Eprom with Embedded Eeprom
Patent: 5,850,092 →
Application: 08/833,925 →
A Memory Under Test Programming and Reading Device
Patent: 6,148,413 →
Application: 08/835,030 →
Circuit for the Generation of a Voltage as a Function of the Conductivity of an Elementary Cell of a Non-Volatile Memory
Patent: 5,801,988 →
Application: 08/835,031 →
Reference Word Line and Data Propagation Reproduction Circuit for Memories Provided with Hierarchical Decoders
Patent: 5,754,483 →
Application: 08/835,033 →
Circuit for the Switching of Supply Voltages in Electrically Programmable and Cancelable Non-Volatile Semiconductor Memory Devices
Patent: 5,754,473 →
Application: 08/835,294 →
Auto-Saving Circuit for Programming Configuration Elements in Non-Volatile Memory Devices
Patent: 5,864,500 →
Application: 08/835,296 →
Pre-Charge Step Determining Circuit of a Generic Bit Line Particularly for Non-Volatile Memories
Patent: 6,061,273 →
Application: 08/835,347 →
Circuits and Methods for Read-Enabling Memory Devices Synchronously Withthe Reaching of the Minimum Functionality Conditions of the Memory Cells and Reading Circuits, Particularly for Non-Volatile Memories
Patent: 5,878,049 →
Application: 08/840,056 →
Redundancy Memory Register
Patent: 5,812,467 →
Application: 08/841,903 →
Method for Detecting Redunded Defective Addresses in a Memory Device with Redundancy
Patent: 5,838,623 →
Application: 08/841,904 →
Semiconductor Memory Device with Row Redundancy
Patent: 5,889,710 →
Application: 08/842,835 →
Sensing Circuitry for Reading and Verifying the Contents of Electrically Programmable/Erasable Non-Volatile Memory Cells
Patent: 5,917,753 →
Application: 08/845,916 →
Biasing Circuit for Uprom Cells with Low Voltage Supply
Patent: 5,859,797 →
Application: 08/846,753 →
Uprom Cell for Low Voltage Supply
Patent: 5,822,259 →
Application: 08/846,755 →
Power on Reset Circuit with Auto Turn Off
Patent: 5,929,674 →
Application: 08/846,757 →
Memory Architecture for Flexible Reading Management, Particularly for Non-Volatile Memories, Having Noise-Immunity Features, Matching Device Performance, and Having Optimized Throughout
Patent: 5,917,768 →
Application: 08/847,385 →
Column Multiplexer
Patent: 5,777,941 →
Application: 08/853,732 →
Electrically Erasable and Programmable Non-Volatile Memory Device with Testable Redundancy Circuits
Patent: 5,999,450 →
Application: 08/853,756 →
Line Decoder for Memory Devices
Patent: 6,018,255 →
Application: 08/862,563 →
Method and Circuit Architecture for Testing a Non-Volatile Memory Device
Patent: 6,081,911 →
Application: 08/865,642 →
Synchronization Signal Generation Circuit and Method
Patent: 5,959,935 →
Application: 08/865,748 →
Integrated Circuit for Generating Initialization Signals for Memory Cell Sensing Circuits
Patent: 5,914,901 →
Application: 08/866,283 →
Method for Verifying Electrically Programmable Non-Volatile Memory Cells of an Electrically Programmable Non-Volatile Memory Device After Programming
Patent: 5,864,503 →
Application: 08/866,531 →
Memory Device with Clocked Column Redundancy
Patent: 5,831,915 →
Application: 08/868,213 →
Semiconductor Memory Device with Clocked Column Redundancy and Time-Shared Redundancy Data Transfer Approach
Patent: 5,968,183 →
Application: 08/868,214 →
Page-Mode Memory Device with Multiple-Level Memory Cells
Patent: 5,757,719 →
Application: 08/869,208 →
Semiconductor Memory Device with Row and Column Redundancy Circuits and a Time-Shared Redundancy Circuit Test Architecture
Patent: 5,867,504 →
Application: 08/869,367 →
Circuit for Transferring Redundancy Data of a Redundancy Circuit Inside a Memory Device by Means of a Time-Shared Approach
Patent: 5,864,562 →
Application: 08/869,859 →
Circuit and Method for Generating a Read Reference Signal for Nonvolatile Memory Cells
Patent: 5,805,500 →
Application: 08/877,921 →
Read Circuit and Method for Nonvolatile Memory Cells with an Equalizing Structure
Patent: 5,886,925 →
Application: 08/877,922 →
Low-Supply-Voltage Nonvolatile Memory Device with Voltage Boosting
Patent: 5,903,498 →
Application: 08/877,927 →
Method and Circuit for Reading Low-Supply-Voltage Nonvolatile Memory Cells
Patent: 6,128,225 →
Application: 08/879,017 →
Clock Circuit for Reading a Mutilevel Non Volatile Memory Cells Device
Patent: 5,986,921 →
Application: 08/883,822 →
Low Noise Output Buffer for Semiconductor Electronic Circuits
Patent: 6,060,753 →
Application: 08/889,653 →
Process for Manufacturing an Integrated Circuit Comprising an Array of Memory Cells
Patent: 5,976,933 →
Application: 08/897,799 →
High Voltage Tolerance Output Stage
Patent: 6,150,844 →
Application: 08/898,811 →
Output Stage for a Memory Device and for Low Voltage Applications
Patent: 6,215,329 →
Application: 08/899,228 →
Bidirectional Charge Pump Generating Either a Positive or Negative Voltage
Patent: 6,184,741 →
Application: 08/900,165 →
Asymmetrical Pulsive Delay Network
Patent: 6,046,619 →
Application: 08/900,424 →
Multilevel Non-Volatile Memory Devices
Patent: 5,999,445 →
Application: 08/916,874 →
Cmos Twin-Tub Negative Voltage Switching Architecture
Patent: 5,994,948 →
Application: 08/921,930 →
Stacked Charge Pump Circuit
Patent: 5,926,059 →
Application: 08/927,391 →
Control Circuit of an Output Buffer
Patent: 5,905,678 →
Application: 08/934,499 →
Neading Circuit for Semiconductor Memory Cells
Patent: 5,883,837 →
Application: 08/940,115 →
Floating Gate Mos Transistor Charge Injection Circuit and Computation Devices Incorporating It
Patent: 5,946,235 →
Application: 08/940,278 →
Method and Circuit for Checking Multilevel Programming of Floating-Gate Nonvolatile Memory Cells Particularly Flash Cells
Patent: 5,880,993 →
Application: 08/941,882 →
Positive Charge Pump
Patent: 6,075,402 →
Application: 08/946,727 →
Circuit for Selectively Enabling One Among a Plurality of Circuit Alternatives of an Integrated Circuit
Patent: 6,100,740 →
Application: 08/957,685 →
Self-Regulated Equalizer, Particularly for Sense Amplifiers
Patent: 5,986,954 →
Application: 08/960,926 →
Protection Circuit for Redundancy Register Set-Up Cells of Electrically Programmable Non-Volatile Memory Devices
Patent: 5,854,762 →
Application: 08/961,368 →
Bicmos Negative Charge Pump
Patent: 6,016,073 →
Application: 08/965,068 →
Method and Circuit for Generating a Synchronizing Atd Signal
Patent: 5,886,949 →
Application: 08/978,665 →
Process for Realizing an Intermediate Dielectric Layer for Enhancing the Planarity in Semiconductor Electronic Devices
Patent: 6,239,042 →
Application: 08/987,454 →
Process for the Repair of Floating-Gate Non-Volatile Memories Damaged by Plasma Treatment
Patent: 5,888,836 →
Application: 08/990,328 →
Process for Depositing a Stratified Dielectric Structure for Enhancing the Planarity of Semiconductor Electronic Devices
Patent: 5,994,231 →
Application: 08/996,920 →
Autoaligned Etching Process for Realizing Word Lines in Memory Devices Integrated Semiconductor Subtrates
Patent: 6,130,165 →
Application: 08/997,499 →
Electronic Memory Device Having Bit Lines with Block Selector Switches
Patent: 5,969,977 →
Application: 08/998,854 →
Folding Top for a Motor Vehicle
Patent: 6,039,382 →
Application: 09/002,599 →
Power-On Reset Circuit for Dual Supply Voltages
Patent: 6,078,201 →
Application: 09/003,474 →
Nmos Negative Charge Pump
Patent: 6,130,572 →
Application: 09/012,331 →
Memory Device with a Memory Cell Array in Triple Well, and Related Manufacturing Process
Patent: 5,990,526 →
Application: 09/027,343 →
Voltage Level Shifter Device, Particulary for a Nonvolatile Memory
Patent: 5,959,902 →
Application: 09/030,604 →
Method and Circuit for Trimming the Internal Timing Conditions of a Semiconductor Memory Device
Patent: 6,009,041 →
Application: 09/032,272 →
Staircase Adaptive Voltage Generator Circuit
Patent: 5,949,666 →
Application: 09/032,282 →
Method and Device for Reading a Non-Erasable Memory Cell
Patent: 6,075,718 →
Application: 09/039,588 →
Device and Method for Increasing the Internal Address of a Memory Device Using Multifunctional Terminals
Patent: 6,115,801 →
Application: 09/049,858 →
Memory Device with Reduced Power Dissipation
Patent: 6,061,286 →
Application: 09/053,720 →
Method and Device for Analog Programming of Non-Volatile Memory Cells
Patent: 6,195,283 →
Application: 09/076,013 →
High Voltage Capacitor
Patent: 6,188,121 →
Application: 09/119,115 →
Process for the Manufacturing of an Electrically Programmable Non-Volatile Memory Device
Patent: 6,194,270 →
Application: 09/130,720 →
Method for Manufacturing a Native Mos P-Channel Transistor with a Process for Manufacturing Non-Volatile Memories
Patent: 6,063,663 →
Application: 09/139,909 →
Method and Circuit for Generating a Gate Voltage in Non-Volatile Memory Devices
Patent: 6,016,271 →
Application: 09/141,250 →
Method and Device for Analog Programming of Flash Eeprom Memory Cells with Autoverify
Patent: 6,081,448 →
Application: 09/162,639 →
Compensated Voltage Regulator
Patent: 5,982,677 →
Application: 09/163,755 →
Controlled Hot-Electron Writing Method for Non-Volatile Memory Cells
Patent: 6,172,908 →
Application: 09/169,239 →
Improved Output Circuit for Integrated Circuits
Patent: 6,153,914 →
Application: 09/170,788 →
Memory Device Generator for Generating Memory Devices with Redundancy
Patent: 6,598,190 →
Application: 09/175,220 →
Method for Parallel Programming of Nonvolatile Memory Devices, in Particular Flash Memories and Eeproms
Patent: 6,069,822 →
Application: 09/181,230 →
Read Circuit for Non-Volatile Memories
Patent: 6,097,633 →
Application: 09/182,843 →
Method for Multilevel Programming of a Nonvolatile Memory, and a Multilevel Nonvolatile Memory
Patent: 6,011,715 →
Application: 09/185,906 →
Method and Circuit for Generating an Atd Signal to Regulate the Access to a Non-Volatile Memory
Patent: 6,075,750 →
Application: 09/186,497 →
Voltage Regulator for Single Feed Voltage Memory Circuits, and Flash Type Memory in Particular
Patent: 6,101,118 →
Application: 09/196,204 →
Multi-Level Memory Circuit with Regulated Writing Voltage
Patent: 6,097,628 →
Application: 09/202,656 →
Multi-Level Memory Circuit with Regulated Reading Voltage
Patent: 6,101,121 →
Application: 09/202,657 →
Self-Test and Correction of Loss of Charge Errors in a Flash Memory, Erasable and Programmable by Sectors Thereof
Patent: 6,275,960 →
Application: 09/212,896 →
Row Decoder Circuit for an Electronic Memory Device, Particularly for Low Voltage Applications
Patent: 6,069,837 →
Application: 09/222,022 →
Method and a Related Circuit for Adjusting the Duration of a Synchronization Signal Atd for Timing the Access to a Non-Volatile Memory
Patent: 6,237,104 →
Application: 09/222,070 →
Esd Protection Network for Circuit Structures Formed in a Semiconductor
Patent: 6,266,222 →
Application: 09/223,621 →
High Voltage Driver Circuit for a Decoding Circuit in Multilevel Non-Volatile Memory Devices
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Interleaved Memory Device for Burst Type Access in Synchronous Read Mode with the Two Semi-Arrays Independently Readable in Random Access Asynchronous Mode
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Charge Pump Booster Device with Transfer and Recovery of the Charge
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Column Decoder Circuit for Page Reading of a Semiconductor Memory
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Process for the Fabrication of Integrated Devices with Reduction of Damage from Plasma
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Circuit Arrangement for the Lowering of the Threshold Voltage of a Diode Configured Transistor
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Biasing Circuit for Multi-Level Memory Cells
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Non-Volatile Memory Matrix Architecture with Vertical Insulation Strips Between Adjacent Memory Blocks.
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Process for Manufacturing a Non-Volatile Memory Cell with a Floating Gate Region Autoaligned to the Isolation and with a High Coupling Coefficient
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Circuit Device for Performing Hierarchic Row Decoding in Non-Volatile Memory Devices
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Conduction Line Decoupling Circuit
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Reading Circuit for Semiconductor Non-Volatile Memories
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Lateral Dmos Transistor with First and Second Drain Electrodes in Respective Contact with High-and Low-Concentration Portions of a Drain Region
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Control Circuit for a Variable-Voltage Regulator of a Nonvolatile Memory with Hierarchical Row Decoding
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Small Size, Low Consumption, Multilevel Nonvolatile Memory
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Control and Timing Structure for a Memory
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Flanged Pipe Fitting
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Control Circuit for an Output Driving Stage of an Integrated Circuit
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Method for Avoiding the Effects of Lack of Uniformity in Trench Isolated Integrated Circuits
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Negative Charge Pump Architecture with Self-Generated Boosted Phases
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Circuit for Generating a Pulse Signal Independent of Voltage and Temperature Variations
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Programming Method for a Multilevel Memory Cell
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Generator Circuit for Voltage Ramps and Corresponding Voltage Generation Method
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Multi-Emitter Bipolar Transistor for Bandgap Reference Circuits
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Method of Programming a Plurality of Memory Cells Connected in Parallel, and a Programming Circuit Therefor
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Memory Device
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Method and Circuit for Dynamic Reading of a Memory Cell, in Particular a Multi-Level Nonvolatile Memory Cell
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Method for Refreshing Stored Data in an Electrically Erasable and Programmable Non-Volatile Memory
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Non-Volatile, Electrically Alterable Semiconductor Memory
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Boost Device for Nonvolatile Memories with an Integrated Stand-by Charge Pump
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Device and Method for Timing the Reading of a Nonvolatile Memory with Reduced Switching Noise
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Device and Method for Automatically Generating an Appropriate Number of Wait Cycles While Reading a Nonvolatile Memory
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Method and Circuit for Timing Dynamic Reading of a Memory Cell with Control of the Integration Time
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Column Multiplexer for Semiconductor Memories
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Method for Error Control in Multilevel Cells with Configurable Number of Stored Bits
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Output Buffer for a Nonvolatile Memory with Output Signal Switching Noise Reduction, and Nonvolatile Memory Comprising the Same
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Output Buffer for a Nonvolatile Memory with Optimized Slew-Rate Control
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High-Efficiency Power Charge Pump Supplying High Dc Output Currents
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Method of Re-Programming an Array of Non-Volatile Memory Cells, in Particular of the nor Architecture Flash Type, After an Erase Operation, and a Corresponding Memory Device
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Memory with Improved Differential Reading System
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Process for Removing Polymers During the Fabrication of Semiconductor Devices
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Eeprom Flash Memory Erasable Line by Line
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Nonvolatile Memory Device with Double Serial/Parallel Communication Interface
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Fast Programming Method for Nonvolatile Memories, in Particular Flash Memories, and Relative Memory Architecture
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Finite State Machine Interface Has Arbitration Structure to Store Command Generated by Internal Circuits During Evaluation Phase of State Machine for Flash Eeprom Device
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Architecture of a Phase-Change Nonvolatile Memory Array
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Manufacturing Process of a Semiconductor Non-Volatile Memory Cell
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Binary Encoding Circuit
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Regulation Method for the Source Terminal Voltage in a Non-Volatile Memory Cell During a Program Phase and Corresponding Program Circuit
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Circuit for Controlling a Reference Node in a Sense Amplifier
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Sense Amplifier Structure for Multilevel Non-Volatile Memory Devices and Corresponding Reading Method
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Decoding Structure for a Memory Device with a Control Code
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Architecture for a Flash-Eeprom Simultaneously Readable in Other Sectors While Erasing and/or Programming One or More Sectors
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Integrated Resistor, Phase-Change Memory Element Including This Resistor, and Process for the Fabrication Thereof
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Device Integrating a Nonvolatile Memory Array and a Volatile Memory Array
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Sublithographic Contact Structure, Phase Change Memory Cell with Optimized Heater Shape, and Manufacturing Method Thereof
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Method of Writing a Group of Data Bytes in a Memory and Memory Device
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Word Line Selector for a Semiconductor Memory
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Contact Structure, Phase Change Memory Cell, and Manufacturing Method Thereof with Elimination of Double Contacts
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Semiconductor Memory with Self-Refresh Capability
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Non-Volatile Memory Device
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Adjustable Frequency Oscillator with Programmable Calibrating Circuit and Related System and Method
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Self-Repair Method for Nonvolatile Memory Devices Using a Supersecure Architecture, and Nonvolatile Memory Device
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Method for Reducing Spurious Erasing During Programming of a Nonvolatile Nrom
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Electrically Erasable and Programmable Non-Volatile Memory Cell
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Voltage Regulator with Very Quick Response
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Voltage Boost Device and Memory System
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Line Selector for a Matrix of Memory Elements
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Automatic Decoding Method for Mapping and Selecting a Non-Volatile Memory Device Having a Lpc Serial Communication Interface in the Available Addressing Area on Motherboards
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Method for Controlling Programming Voltage Levels of Non-Volatile Memory Cells, the Method Tracking the Cell Features, and Corresponding Voltage Regulator
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Memory Device Accessible with Different Communication Protocols
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Circuit for Biasing an Input Node of a Sense Amplifier with a Pre-Charge Stage
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Method for Detecting a Resistive Path or a Predetermined Potential in Non-Volatile Memory Electronic Devices
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Process for Manufacturing an Array of Cells Including Selection Bipolar Junction Transistors
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Array of Cells Including a Selection Bipolar Transistor and Fabrication Method Thereof
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Structure for Updating a Block of Memory Cells in a Flash Memory Device with Erase and Program Operation Reduction
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Semiconductor Memory with Embedded Dram
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Memory Device Composed of a Plurality of Memory Chips in a Single Package
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Method and Device for Programming an Electrically Programmable Non-Volatile Semiconductor Memory
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Memory System Comprising a Semiconductor Memory
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Structure and Method for Detecting Errors in a Multilevel Memory Device with Improved Programming Granularity
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Method for Manufacturing Non-Volatile Memory Cells on a Semiconductor Substrate
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Fast Page Programming Architecture and Method in a Non-Volatile Memory Device with an Spi Interface
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Non Volatile Memory Device Including a Predetermined Number of Sectors
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Voltage Supply Distribution Architecture for a Plurality of Memory Modules
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Method for Manufacturing Non-Volatile Memory Cells on a Semiconductive Substrate
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Parallel Sense Amplifier with Mirroring of the Current to Be Measured into Each Reference Branch
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Method for Soft-Programming an Electrically Erasable Nonvolatile Memory Device, and an Electrically Erasable Nonvolatile Memory Device Implementing the Soft-Programming Method
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Gate Voltage Regulation System for a Non Volatile Memory Cells Programming and/or Soft Programming Phase
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Method for Reading a Nonvolatile Memory Device and Nonvolatile Memory Device Implementing the Reading Method
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Method for Generating a Reference Current for Sense Amplifiers and Corresponding Generator
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Redundancy Scheme for a Memory Integrated Circuit
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Publication: US 2005/0030809
Sense Amplifier with Equalizer
Patent: 7,136,305 →
Application: 10/913,788 →
Publication: US 2005/0063236
Bit Line Discharge Control Method and Circuit for a Semiconductor Memory
Patent: 7,257,039 →
Application: 10/971,776 →
Publication: US 2005/0169095
Charge Pump Circuit with a Brief Settling Time and High Output Voltage Regulation Precision
Patent: 7,176,748 →
Application: 10/982,528 →
Publication: US 2005/0127982
Integrated Memory Device with Multi-Sector Selection Commands
Patent: 7,457,908 →
Application: 10/984,372 →
Publication: US 2005/0157553
Fast Reading, Low Consumption Memory Device and Reading Method Thereof
Patent: 7,203,087 →
Application: 11/018,550 →
Publication: US 2005/0185572
Sequential Program-Verify Method with Result Buffering
Patent: 7,184,310 →
Application: 11/093,012 →
Publication: US 2005/0232019
Synchronous Memory Device with Reduced Power Consumption
Patent: 7,366,012 →
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Publication: US 2005/0270892
Distribution of an Electric Quantity Through a Circuit
Patent: 7,521,989 →
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Publication: US 2006/0018067
Sensing Circuit for a Semiconductor Memory
Patent: 7,184,348 →
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Publication: US 2006/0023531
Nonvolatile Phase Change Memory Device and Biasing Method Therefor
Patent: 7,269,080 →
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Publication: US 2006/0056265
Row Decoder for Nand Memories
Patent: 7,180,786 →
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Publication: US 2006/0050575
Memory Device with Unipolar and Bipolar Selectors
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Publication: US 2006/0062051
Memory Device and Method for Operating the Same with High Rejection of the Noise on the High-Voltage Supply Line
Patent: 7,324,379 →
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Publication: US 2006/0171204
Memory Device
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Application: 11/249,763 →
Publication: US 2006/0083077
Memory Device
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Publication: US 2006/0083078
Non-Volatile Memory Electronic Device with Nand Structure Being Monolithically Integrated on Semiconductor
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Publication: US 2006/0227609
Phase Change Memory Cell with Junction Selector and Manufacturing Method Thereof
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Publication: US 2006/0158928
Exploiting a Statistical Distribution of the Values of an Electrical Characteristic in a Population of Auxiliary Memory Cells for Obtaining Reference Cells
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Memory Device with Time-Shifting Based Emulation of Reference Cells
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Memory Device with a Ramp-Like Voltage Biasing Structure and Reduced Number of Reference Cells
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Phase Change Memory Cell with Tubular Heater and Manufacturing Method Thereof
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Flash Memory Device with Improved Management of Protection Information
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Flash Memory Device with Nand Architecture with Reduced Capacitive Coupling Effect
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Semiconductor Memory Device with a Page Buffer Having an Improved Layout Arrangement
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Related Assignments (7)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Patent Security Agreement Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
Corrective Assignment to Correct the Replace Erroneously Filed Patent #7358718 with the Correct Patent #7358178 Previously Recorded on Reel 038669 Frame 0001. Assignor(S) Hereby Confirms the Security Interest. Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
Security Interest Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
Release of Security Interest Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
Release of Security Interest Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →