Device integrating a nonvolatile memory array and a volatile memory array
View Patent ↗An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.
1. An integrated circuit, comprising:
a first rewritable memory cell having a first storage capacitor and configured to operate only as a nonvolatile memory cell; and
a second memory cell having a second storage capacitor and configured to operate as a volatile memory cell wherein:
the first storage capacitor comprises a first ferro-electric layer; and
the second storage capacitor comprises a second ferro-electric layer that is thicker than the first ferro-electric layer.
2. The integrated circuit of claim 1 wherein the first and second storage capacitors each comprise a respective ferro-electric capacitor.
3. The integrated circuit of claim 1 wherein:
the first storage capacitor comprises a first dielectric; and
the second storage capacitor comprises a second dielectric that is thicker than the first dielectric.
4. The integrated circuit of claim 1 wherein the nonvolatile memory cell has a structure that is the same as the structure of the volatile memory cell.
5. A method, comprising:
in a mode of operation, storing data in a first memory cell on an integrated circuit in a nonvolatile manner by applying a first voltage to the cell, the absolute value of the first voltage exceeding an absolute value of a switching voltage of the first cell, the first memory cell having one and only one capacitor;
in the same mode of operation, storing different data in the first memory cell in a nonvolatile manner; and
in the same mode of operation, storing data in a second memory cell on the integrated circuit in a volatile manner by applying a second voltage to the cell, the absolute value of the second voltage being less than an absolute value of the switching voltage of the second cell.
6. The method of claim 5 wherein the first and second memory cells each comprise a respective ferro-electric capacitor.
7. The integrated circuit of claim 4 wherein the second memory cell is configured to operate only as a volatile memory cell.
8. A method for reading/writing a memory having a plurality of cells including a capacitor, which is formed by a first electrode, a second electrode, and by a ferro-electric material set between said first electrode and said second electrode, the method comprising the steps of:
during an operational mode of the memory, reading/writing a first one of said cells in a volatile manner by,
bringing said first cell into a first stable state, and
supplying to said first cell a read/write voltage in absolute value lower than switching voltages of said cell, said first cell having one and only one capacitor; and
during the same operational mode of the memory, reading/writing a second one of said cells in a nonvolatile manner by,
bringing said second cell into a first stable state, and
supplying to said second cell a read/write voltage in absolute value higher than switching voltages of said second cell, said second cell having one and only one capacitor.
9. A method, comprising:
during a mode of operation, storing data in a first memory cell in a nonvolatile manner, the first memory cell disposed on an integrated circuit and including a nonvolatile storage capacitor having a portion that is disposed in a layer of the integrated circuit;
during the same mode of operation, storing different data in the first memory cell in a nonvolatile manner; and
during the same mode of operation, storing data in a second memory cell in a volatile manner, the second memory cell disposed on the integrated circuit and including a volatile storage capacitor having a portion that is disposed in the layer of the integrated circuit.
10. A method, comprising:
in a mode of operation, storing data in a first memory cell on an integrated circuit in a nonvolatile manner by applying a first voltage to the cell, the absolute value of the first voltage exceeding an absolute value of a switching voltage of the first cell;
in the same mode of operation, storing different data in the first memory cell in a nonvolatile manner; and
in the same mode of operation, storing data in a second memory cell on the integrated circuit in a volatile manner by applying a second voltage to the cell, the absolute value of the second voltage being less than an absolute value of the switching voltage of the second cell, the second memory cell having one and only one capacitor.